SHUNT-COMPENSATED TRANSISTOR STAGE

Domain	Definition
Electrical Engineering	A wide-band class-A amplifier stage with a reactive circuit in parallel with input or output to reduce high-frequency gain fall-off, or phase shift, or both. Source: European Union. (references)
Source: compiled by the editor from various references; see credits.

Language		Translations for "SHUNT-COMPENSATED TRANSISTOR STAGE"; alternative meanings/domain in parentheses.
Danish		parallelkoblingskompenseret transistortrin. (various references)

Dutch		met shunt gecompenseerde transistortrap. (various references)

French		étage � transistors compensés en parallèle. (various references)

German		parallelschaltungskompensierte Transistorstufe. (various references)

Greek		βαθμίδα τρανζίστορ με παράλληλη αντιστάθμιση. (various references)

Italian		stadio a transistori compensato in parallelo. (various references)

Pig Latin		unt-compensatedshay ansistortray agestay

Portuguese		andar transistorizado compensado em paralelo. (various references)

Spanish		etapa a transistores compensada en paralelo. (various references)

Swedish		parallellkompenserat transistorsteg. (various references)
Source: compiled by the editor from various translation references.

Specialty Definition: SHUNT-COMPENSATED TRANSISTOR STAGE