Copyright © Philip M. Parker, INSEAD. Terms of Use.
| Domain | Definition |
Computing | Interrupt priority level The Motorola 68000 family of processors can be at an interrupt priority level from 0 (no interrupt in progress) up to 7. While the processor is handling an interrupt at one level, it will ignore other interrupts at that level or lower. (1994-11-23). Source: The Free On-line Dictionary of Computing. |
Source: compiled by the editor from various references; see credits. | |
Hexadecimal (or equivalents, 770AD-1900s) (references)49 4E 54 45 52 52 55 50 54 50 52 49 4F 52 49 54 59 4C 45 56 45 4C |
| Leonardo da Vinci (1452-1519; backwards) (references)
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Binary Code (1918-1938, probably earlier) (references)01001001 01001110 01010100 01000101 01010010 01010010 01010101 01010000 01010100 00100000 01010000 01010010 01001001 01001111 01010010 01001001 01010100 01011001 00100000 01001100 01000101 01010110 01000101 01001100 |
HTML Code (1990) (references)I N T E R R U P T   P R I O R I T Y   L E V E L |
ISO 10646 (1991-1993) (references)0049 004E 0054 0045 0052 0052 0055 0050 0054 0050 0052 0049 004F 0052 0049 0054 0059 004C 0045 0056 0045 004C |
Encryption (beginner's substitution cypher): (references)4348543952525550542505243495243545924639563946 |
| 1. Orthography 2. Bibliography |
Copyright © Philip M. Parker, INSEAD. Terms of Use.
