Copyright © Philip M. Parker, INSEAD. Terms of Use.

DYNAMIC RANDOM ACCESS MEMORY

Specialty Definition: DYNAMIC RANDOM ACCESS MEMORY

DomainDefinition

Computing

Dynamic random access memory (DRAM) A type of semiconductor memory in which the information is stored in capacitors on a MOS integrated circuit. Typically each bit is stored as an amount of electrical charge in a storage cell consisting of a capacitor and a transistor. Due to leakage the capacitor discharges gradually and the memory cell loses the information. Therefore, to preserve the information, the memory has to be refreshed periodically. Despite this inconvenience, the DRAM is a very popular memory technology because of its high density and consequent low price. The first commercially available DRAM chip was the Intel 1103, introduced in 1970. The early DRAM chips up to a 16k x 1 (16384 locations of one bit each) model needed 3 supply voltages (+5V, -5V and +12V). Beginning with the 64 kilobit chips, charge pumps were included on-chip to create the necessary supply voltages out of a single +5V supply. This was necessary to fit the device into a 16-pin DIL package, which was the preferred package at the time, and also made them easier to use. To reduce the pin count, thereby helping miniaturisation, DRAMs generally had a single data line which meant that a computer with an N bit wide data bus needed a "bank" of (at least) N DRAM chips. In a bank, the address and control signals of all chips were common and the data line of each chip was connected to one of the data bus lines. Beginning with the 256 kilobit DRAM, a tendency towards surface mount packaging arose and DRAMs with more than one data line appeared (e.g. 64k x 4), reducing the number of chips per bank. This trend has continued and DRAM chips with up to 36 data lines are available today. Furthermore, together with surface mount packages, memory manufacturers began to offer memory modules, where a bank of memory chips was preassembled on a little printed circuit board (SIP = Single Inline Pin Module, SIMM = Single Inline Memory Module, DIMM = Dual Inline Memory Module). Today, this is the preferred way to buy memory for workstations and personal computers. DRAM bit cells are arranged on a chip in a grid of rows and columns where the number of rows and columns are usually a power of two. Often, but not always, the number of rows and columns is the same. A one megabit device would then have 1024 x 1024 memory cells. A single memory cell can be selected by a 10-bit row address and a 10-bit column address. To access a memory cell, one entire row of cells is selected and its contents are transferred into an on-chip buffer. This discharges the storage capacitors in the bit cells. The desired bits are then read or written in the buffer. The (possibly altered) information is finally written back into the selected row, thereby refreshing all bits (recharging the capacitors) in the row. To prevent data loss, all bit cells in the memory need to be refreshed periodically. This can be done by reading all rows in regular intervals. Most DRAMs since 1970 have been specified such that one of the rows needs to be refreshed at least every 15.625 microseconds. For a device with 1024 rows, a complete refresh of all rows would then take up to 16 ms; in other words, each cell is guaranteed to hold the data for 16 ms without refresh. Devices with more rows have accordingly longer retention times. Many varieties of DRAM exist today. They differ in the the way they are interfaced to the system - the structure of the memory cell itself is essentially the same. "Traditional" DRAMs have multiplexed address lines and separate data inputs and outputs. There are three control signals: RAS\ (row address strobe), CAS\ (column address strobe), and WE\ (write enable) (the backslash indicates an active low signal). Memory access procedes as follows: 1. The control signals initially all being inactive (high), a memory cycle is started with the row address applied to the address inputs and a falling edge of RAS\ . This latches the row address and "opens" the row, transferring the data in the row to the buffer. The row address can then be removed from the address inputs since it is latched on-chip. 2. With RAS\ still active, the column address is applied to the address pins and CAS\ is made active as well. This selects the desired bit or bits in the row which subsequently appear at the data output(s). By additionally activating WE\ the data applied to the data inputs can be written into the selected location in the buffer. 3. Deactivating CAS\ disables the data input and output again. 4. Deactivating RAS\ causes the data in the buffer to be written back into the memory array. Certain timing rules must be obeyed to guarantee reliable operation. 1. RAS\ must remain inactivate for a while before the next memory cycle is started to provide sufficient time for the storage capacitors to charge (Precharge Time). 2. It takes some time from the falling edge of the RAS\ or CAS\ signals until the data appears at the data output. This is specified as the Row Access Time and the Column Access Time. Current DRAM's have Row Access Times of 50-100 ns and Column Access Times of 15-40 ns. Speed grades usually refer to the former, more important figure. Note that the Memory Cycle Time, which is the minimum time from the beginning of one access to the beginning of the next, is longer than the Row Access Time (because of the Precharge Time). Multiplexing the address pins saves pins on the chip, but usually requires additional logic in the system to properly generate the address and control signals, not to mention further logic for refresh. Therefore, DRAM chips are usually preferred when (because of the required memory size) the additional cost for the control logic is outweighed by the lower price. Based on these principles, chip designers have developed many varieties to improve performance or ease system integration of DRAMs: PSRAMs (Pseudo Static Random Access Memory) are essentially DRAMs with a built-in address multiplexor and refresh controller. This saves some system logic and makes the device look like a normal SRAM. This has been popular as a lower cost alternative for SRAM in embedded systems. It is not a complete SRAM substitute because it is sometimes busy when doing self-refresh, which can be tedious. Nibble Mode DRAM can supply four successive bits on one data line by clocking the CAS\ line. Page Mode DRAM is a standard DRAM where any number of accesses to the currently open row can be made while the RAS signal is kept active. Static Column DRAM is similar to Page Mode DRAM, but to access different bits in the open row, only the column address needs to be changed while the CAS\ signal stays active. The row buffer essentially behaves like SRAM. Extended Data Out DRAM (EDO DRAM) can continue to output data from one address while setting up a new address, for use in pipelined systems. DRAM used for Video RAM (VRAM) has an additional long shift register that can be loaded from the row buffer. The shift register can be regarded as a second interface to the memory that can be operated in parallel to the normal interface. This is especially useful in frame buffers for CRT displays. These frame buffers generate a serial data stream that is sent to the CRT to modulate the electron beam. By using the shift register in the VRAM to generate this stream, the memory is available to the computer through the normal interface most of the time for updating the display data, thereby speeding up display data manipulations. SDRAM (Synchronous DRAM) adds a separate clock signal to the control signals. It allows more complex state machines on the chip and high speed "burst" accesses that clock a series of successive bits out (similar to the nibble mode). CDRAM (Cached DRAM) adds a separate static RAM array used for caching. It essentially combines main memory and cache memory in a single chip. The cache memory controller needs to be added externally. RDRAM (Rambus DRAM) changes the system interface of DRAM completely. A byte-wide bus is used for address, data and command transfers. The bus operates at very high speed: 500 million transfers per second. The chip operates synchronously with a 250MHz clock. Data is transferred at both rising and falling edges of the clock. A system with signals at such frequencies must be very carefully designed, and the the signals on the Rambus Channel use nonstandard signal levels, making it incompatible with standard system logic. These disadvantages are compensated by a very fast data transfer, especially for burst accesses to a block of successive locations. A number of different refresh modes can be included in some of the above device varieties: RAS\ only refresh: a row is refreshed by an ordinary read access without asserting CAS\. The data output remains disabled. CAS\ before RAS\ refresh: the device has a built-in counter for the refresh row address. By activating CAS\ before activating RAS\, this counter is selected to supply the row address instead of the address inputs. Self-Refresh: The device is able to generate refresh cycles internally. No external control signal transitions other than those for bringing the device into self-refresh mode are needed to maintain data integrity. (1996-07-11). Source: The Free On-line Dictionary of Computing.

Source: compiled by the editor from various references; see credits.

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Specialty Definition: Dynamic random access memory

(From Wikipedia, the free Encyclopedia)

DRAM is a type of random access memory that stores each bit of data in a separate capacitor. The amount of electric charge stored in the capacitor determines whether the bit is considered 1 or 0. As leakage causes the charge on a capacitor to decay, the information gets lost eventually, unless the charge is refreshed periodically. This puts DRAM in the class of volatile memory devices.

Refresh logic is commonly used with DRAMs to automate the periodic refresh. This makes the circuit more complicated, but the drawback is usually outweighed by the fact that capacitors are cheap and small, so high-density, low-power memory chips can be made using this technology. The alternative to DRAM is SRAM.

An important feature of DRAMs is called address multiplexing. This technique splits the address in half and feeds each half in turn to the chip on the same set of pins. Therefore a DRAM needs only half as many address pins as an SRAM of the same capacity, allowing it to be produced in a smaller, cheaper package.

Many microprocessors include control logic for DRAMs, relieving the circuit designer from the need to provide address multiplexing logic.

Designing with DRAM

The address multiplexing mentioned above is the key to understanding DRAM. The chip has a large array of memory capacitors that are arranged in rows and columns. To read one location in the array, the control circuit first calculates its row number, which it places on the DRAM's address pins. It then toggles the row address select (RAS) pin, causing the DRAM to read the row address. Internally, the DRAM connects the selected row to a bank of amplifiers called sense amplifiers, which read the contents of all the capacitors in the row. The control circuit then places the column number of the desired location on the same address pins, and toggles the column address select (CAS) pin, causing the DRAM to read the column address. The DRAM uses this to select the output of the sense amplifier corresponding to the selected column. After a delay called the CAS access time, this output is presented to the outside world on the DRAM's data I/O pin.

To write data to the DRAM, the control logic uses the same two-step addressing method, but instead of reading the data from the chip at the end of the operation, it provides data to the chip at the start of the operation.

After a read or write operation, the control circuit returns the RAS and CAS pins to their original states to ready the DRAM for its next operation. The DRAM requires a certain interval called the precharge interval between operations.

Once the control circuit has selected a particular row, it can select several columns in succession by placing different column addresses on the address pins, toggling CAS each time, while the DRAM keeps the same row activated. This is quicker than accessing each location using the full row-column procedure. This method is useful for retrieving microprocessor instructions, which tend to be stored at successive addresses in memory.

The above description is for a one-bit DRAM. Many DRAMs are multibit devices (often four or eight bits), having a number of storage arrays operating simultaneously. Each array is attached to its own data I/O pin, allowing multiple bits of data to be transferred on each read or write. This is logically equivalent to having multiple one-bit DRAMs operating in tandem, but uses less space since all the arrays share the same address and control pins.

Special Types of DRAM

Fast page mode DRAM

Fast page mode DRAM is also called FPM DRAM or Page mode DRAM or Fast page mode memory or Page mode memory. In many applications, data is often transferred to and from DRAM in bursts to consecutive addresses. Fast page mode DRAM simplifies this type of operation by providing an automatic column counter. The controller selects a row (also called a page) and column, as with plain DRAM, and reads or writes the selected location. The DRAM then automatically increments the column address, allowing the controller to access the next location without having to supply a new address. This saves time, and increases the performance of the system when reading or writing bursts of data.

Extended data out (EDO) DRAM

EDO DRAM is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved speed.

Synchronous Dynamic RAM (SDRAM)

SDRAM is an improved type of DRAM. Whilst DRAM has an asynchronous interface, meaning that it reacts immediately to changes in its control inputs, SDRAM has a synchronous interface, meaning that it waits for a clock pulse before responding to its control inputs. The clock is used to drive an internal finite state machine that can pipeline incoming commands. This allows the chip to have a more complex pattern of operation than plain DRAM.

Pipelining means that the chip can accept a new command before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears a fixed number of clock pulses after the read command. It is not necessary to wait for the data to appear before sending the next command. This delay is called the latency, and is an important parameter to be considered when purchasing SDRAM for your computer.

SDRAM has now (2000s) replaced plain DRAM in modern computers, because of its greater speed.

Double data rate (DDR) SDRAM

Double data rate (DDR) SDRAM is a later development of SDRAM. All types of SDRAM use a clock signal that is a square wave. This means that the clock alternates regularly between one voltage (low) and another (high), usually millions of times per second. Plain SDRAM, like most synchronous logic circuits, acts on the low-to-high transition of the clock and ignores the opposite transition. DDR SDRAM acts on both transitions, thereby halving the required clock rate for a given data transfer rate.

Rambus DRAM (RDRAM)

Rambus DRAM (RDRAM) is internally similar to DDR SDRAM, but uses a special method of signalling developed by the Rambus Company that allows faster clock speeds. RDRAM chips are packaged on modules called RIMMs, which are not compatible with the DIMMs used for plain SDRAM. The Rambus technology has now been taken over by Intel.

Video DRAM (VRAM)

VRAM is a dual-ported version of DRAM formerly used in graphics adaptors. It is now amost obsolete, having been superseded by SDRAM and SGRAM. VRAM has two paths (or ports) to its memory array that can be used simultaneously. The first port, the DRAM port, is accessed as with plain DRAM. The second port, the video port, is read-only, and is dedicated to feeding a fast stream of data to the display. To use the video port, the controller first uses the DRAM port to select the row of the memory array that is to be displayed. The VRAM then copies that entire row to an internal shift-register. The controller can then continue to use the DRAM port for drawing objects on the display. Meanwhile, the controller feeds a clock called the shift clock (SCLK) to the VRAM's video port. Each SCLK pulse causes the VRAM to deliver the next item of data, in strict address order, from the shift-register to the video port. For simplicity, the graphics adaptor is usually designed so that the contents of a row, and therefore the contents of the shift-register, corresponds to a complete horizontal line on the display.

Synchronous graphics RAM (SGRAM)

It is a specialised form of SDRAM for graphics adaptors. It adds functions such as bit masking (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour).

Pseudostatic RAM (PSRAM)

It is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM (SRAM). It combines the high density of DRAM with the ease of use of true SRAM.

Source: adapted by the editor from Wikipedia, the free encyclopedia under a copyleft GNU Free Documentation License (GFDL) from the article "Dynamic random access memory."

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Crosswords: DYNAMIC RANDOM ACCESS MEMORY

Specialty definitions using "DYNAMIC RANDOM ACCESS MEMORY": Column Address Strobe ♦ D-RAM, dynamic RAM ♦ EDO DRAM, EDO memory, EDO RAM, EDRAM, Enhanced Dynamic Random Access Memory, Extended Data Out Random Access Memory ♦ Fast Page Mode Dynamic Random Access Memory, FP/M, FPM, FPM DRAM ♦ Page Mode DRAM, Page Mode Dynamic Random Access Memory ♦ SDRAM, Single Data Rate Random Access Memory, Single Data Rate Synchronous Dynamic Random Access Memory, static random access memory, Synchronous DRAM, Synchronous Dynamic Random Access Memory. (references)

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Commercial Usage: DYNAMIC RANDOM ACCESS MEMORY

DomainTitle

Books

  • Dynamic Random Access Memory (DRAM) [DOWNLOAD: PDF] (reference)

    (more book examples)

Source: compiled by the editor from various references; see credits.

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Expressions: DYNAMIC RANDOM ACCESS MEMORY

Expressions using "DYNAMIC RANDOM ACCESS MEMORY": enhanced Dynamic Random Access Memory ♦ extended Data Out Dynamic Random Access Memory ♦ fast Page Mode Dynamic Random Access Memory ♦ page Mode Dynamic Random Access Memory ♦ single Data Rate Synchronous Dynamic Random Access Memory ♦ synchronous Dynamic Random Access Memory. Additional references.

Source: compiled by the editor from various references; see credits.

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Modern Translation: DYNAMIC RANDOM ACCESS MEMORY

Language Translations for "DYNAMIC RANDOM ACCESS MEMORY"; alternative meanings/domain in parentheses.

Danish

  

dynamisk RAM (DRAM, dynamic RAM), dynamisk lager med direkte tilgang (DRAM, dynamic RAM). (various references)

   

Dutch

  

dynamische RAM (DRAM, dynamic RAM), dynamisch RAM-geheugen (DRAM, dynamic RAM). (various references)

   

Finnish

  

dynaaminen hakumuisti (DRAM, dynamic RAM), DRAM (DRAM, dynamic RAM). (various references)

   

French

  

MEVD (dynamic RAM), mémoire vive dynamique (dynamic RAM), mémoire RAM dynamique (dynamic RAM). (various references)

   

German

  

dynamisches RAM (DRAM, dynamic RAM), dynamischer Schreib-/Lesespeicher (DRAM, dynamic RAM), dynamischer RAM-Speicher (DRAM, dynamic RAM). (various references)

   

Greek 

  

δυναμική μνήμη (circulating storage, circulating store, cyclic storage, cyclic store, DRAM, dynamic memory, dynamic RAM, dynamic storage, dynamic store). (various references)

   

Italian

  

DRAM (DRAM, d-RAM, dynamic RAM), memoria RAM dinamica (DRAM, d-RAM, dynamic RAM), memoria dinamica ad accesso casuale (DRAM, d-RAM), memoria di accesso casuale dinamica (DRAM, dynamic RAM). (various references)

   

Pig Latin

  

ynamicday andomray accessay emorymay

   

Portuguese

  

memória viva dinâmica (DRAM, dynamic RAM). (various references)

   

Spanish

  

memoria RAM dinámica (DRAM, dynamic RAM). (various references)

   

Swedish

  

dynamiskt RAM-minne (DRAM, dynamic RAM), dynamiskt direktminne (DRAM, dynamic RAM). (various references)

Source: compiled by the editor from various translation references.

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INDEX

1. Crosswords
2. Usage: Commercial
3. Expressions
4. Translations: Modern 		5. Bibliography


  

Copyright © Philip M. Parker, INSEAD. Terms of Use.