BRANCH DELAY SLOT

In computer architecture, a branch delay slot is a single cycle delay that comes after a conditional branch instruction has begun execution, but before the branch condition has been resolved, and the branch target address has been computed. It is a feature of several RISC designs, such as the SPARC.

The goal of a pipelined architecture is to keep the pipeline full of instructions at all times. The branch delay slot is a side-effect of pipelined architectures due to the fact that the branch would not be resolved until the instruction has worked its way through the pipeline. A simple design would insert stalls into the pipeline after a branch instruction until the new branch target address is computed and loaded into the program counter. Each cycle where a stall is inserted is considered one branch delay slot.

The number of branch delay slots in a particular pipeline implementation is dictated by the number of pipeline stages, the presence of register forwarding, what stage of the pipeline the branch conditions are computed, whether or not a branch target buffer (BTB) is used and many other factors.

By using branch prediction techniques and speculative execution, many of these branch delay slots are efficiently utilitized, reducing the performance penalty incurred by these branch instructions.