IBM 1620

The 1620's Architecture

It was a variable "word" length decimal (BCD) computer with a memory that could hold anything from 20,000 to 60,000 decimal digits increasing in 20,000 decimal digit increments. While the 5-digit addresses could have addressed 100,000 decimal digits, no machine larger than 60,000 decimal digits was ever built.

Memory was accessed 2 decimal digits (Even-Odd digit pair for numeric data or 1 Alphameric character for text data) at the same time. Each decimal digit was 6-bits, composed of an odd parity Check bit, a Flag bit, and 4 BCD bits for the value of the digit in the following format:

  C F 8 4 2 1

• In the least significant digit it was set to indicate a negative number (signed magnitude).
• It was set to mark the most significant digit of a number.
• In the least significant digit of 5-digit addresses it was set for indirect addressing.
• In the middle 3 digits of 5-digit addresses (on the 1620 II) they were set to select one of 7 index registers.

  C F 8 4 2 1
      1 0 1 0  -  Record Mark (right most end of record)
      1 1 0 0  -  Numeric Blank (blank for punched card output formatting)
      1 1 1 1  -  Group Mark (right most end of a group of records for disk I/O)

Fixed point data "words" could be any size from 2 decimal digits up to all of memory not used for other purposes.

Floating point data "words" (using the hardware floating point option) could be any size from 4 decimal digits up to 102 decimal digits (2 digits for the exponent and 2 to 100 digits for the mantissa).

The machine had no programmer accessible registers: all operations were memory to memory (including the index registers of the 1620 II).

There were two models of the 1620, having totally different implementations:

• IBM 1620 I
• IBM 1620 II

• IBM 1621 - Paper tape reader
• IBM 1622 - Punch card reader/punch
• IBM 1624 - Paper tape punch
• IBM 1626 - Plotter controller
• IBM 1627 - Plotter
• IBM 1311 - Disk drive
• IBM 1443 - Printer, flying type bar

Development History

In 1958 IBM assembled a team at the Poughkeepsie, New York development laboratory to study the "small scientific market". Initially the team consisted of Wayne Winger (Manager), Robert C. Jackson, and William H. Rhodes.

The competing computers in this market were the Librascope LGP-30 and the Bendix G-15, both were drum memory machines and it was concluded that IBM could offer nothing really new in that area. To compete effectively would require use of technologies that IBM had developed for larger computers, yet the machine would have to be produced at the least possible cost.

To meet this objective, the team set the following requirements:

• Core memory
• Restricted instruction set
  • No divide or floating point instructions, use subroutines in the "general program package"
• Wherever possible replace hardware with existing logical machine functions
  • No arithmetic circuits, use tables in core memory
• Least expensive Input/Output possible
  • No punch cards, use paper tape
  • No printer, use operators console typewriter

The team expanded with the addition of Anne Deckman, Kelly B. Day, William Florac, and James Brenza. They completed the CADET prototype in the spring of 1959.

Meanwhile the San Jose, California facility was working on a proposal of its own. IBM could only build one of the two and the Poughkeepsie proposal won because "the San Jose version is top of the line and not expandable, while your proposal has all kinds of expansion capability - never offer a machine that cannot be expanded".

Management was not entirely convinced that core memory could be made to work in small machines, so Gerry Ottaway was loaned to the team to design a drum memory as a backup. During acceptance testing by the Product Test Lab repeated core memory failures were encountered and it looked likely that management's predictions would come true. However at the last minute it was found that the fan used to blow hot air through the core stack was malfunctioning, causing the core to pick up noise pulses and fail to read correctly. After the fan problem was fixed there were no further problems with the core memory and the drum memory design effort was discontinued as unnecessary.

IBM 1620 Model I Level A (prototype), as it appeared in the IBM announcement of the machine.

Following announcement of the IBM 1620 on October 22, 1959, due to an internal reorganization of IBM, it was decided to transfer the computer from the Data Processing Division at Poughkeepsie (large scale mainframe computers only) to the General Products Division at San Jose (small computers and support products only) for manufacturing.

Following transfer to San Jose, someone there suggested that the code name CADET actually stood for "Can't Add, Doesn't Even Try." This stuck and became very well known among users of the 1620.

• Model I
  • Level A; prototype.
    • All flip flops in the design were transistorized versions of the original Eccles-Jordan trigger circuit. While this machine was fully functional, it was found that the capacitor coupling used in these proved troublesome in the noisy signal environment of relays and timing cam driven switches used to drive the console typewriter. This necessitated a complete redesign of the machine to use S-R flip flops instead (except for two triggers used to generate clocks for the S-R flip flops). However usage of the term Trigger was retained in all the documentation when referring to a flip flop.
    • This is the only level using a one piece vertical control panel, when the design was transferred from Poughkeepsie to San Jose it was redesigned to the two piece angled control panel used on all production models.
  • Level B; first production.
    • This is the only level using a burnished aluminum lower control panel, later levels finished this panel with white.
  • Level C; introduction of 1622 card reader/punch.
  • Level D; introduction of 1311 disk drives.
  • Level E
  • Level F; introduction of Floating Point option.
  • Level G; final version of the Model I
• Model II (no information on "Levels" available at this time)
• Model III
  • Work was begun on a 1620 Model III in year-TBD, but the project was quickly canceled as IBM wanted to promote sales of their new System/360 and discontinue the old lines.

Patents

• 3,049,295 - Multiplying Computer
  • Patent filed: December 20, 1960
  • Patent issued: August 14, 1962
  • Inventors
    • William H. Rhodes
    • James G. Brenza
    • Wayne D. Winger
    • Robert C. Jackson
  • Claims and prior art references
    • 21 claims
    • No prior art
  • Diagrams and Text
    • 156 sheets of diagrams (Describes 1620 in full details.)
    • 31 sheets of text
• 3,199,085 - Computer with Table Lookup Arithmetic Unit Feature
  • Patent filed: December 20, 1960
  • Patent issued: August 3, 1965
  • Inventors
    • William H. Rhodes
    • James G. Brenza
    • Wayne D. Winger
  • Claims and prior art references
    • 21 claims
    • 5 prior art
  • Diagrams and Text
    • 156 sheets of diagrams (Describes 1620 in full details.)
    • 31 sheets of text
• 3,328,767 - Compact Data Lookup Table
  • Patent filed: December 31, 1963
  • Patent issued: June 27, 1967
  • Inventors
    • Gerald H. Ottaway
  • Claims and prior art references
    • 11 claims
    • 5 prior art
  • Diagrams and Text
    • 5 sheets of diagrams
    • 4 sheets of text
• 3,239,654 - Dividing Computer
  • Patent filed: February 8, 1961
  • Patent issued: March 8, 1966
  • Inventors
    • Robert C. Jackson
    • William A. Florac
    • Wayne D. Winger
  • Claims and prior art references
    • 9 claims
    • 1 prior art
    • 3 publications
  • Diagrams and Text
    • 13 sheets of diagrams
    • 19 sheets of text

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