DQPSK delay detection circuit that produces stable clock signal in response to both I and Q signals

Year	Description
1993	Invention patented by Kazuyoshi Nakaya on November 22th, 1993. Abstract: A DQPSK delay detection circuit is provided that can securely reproduce stable clock signal. An absolute value circuit ABS(14) calculates an absolute value of I signal. An absolute value circuit ABS(15) calculates an absolute value of Q signal. Subtraction circuit(16) generates a P signal according to the difference between the absolute values of I signal and Q signal. Zero-cross detection circuit(11) detects zero-cross timing of the P signal to input it as a timing signal to the DPLL(64). The zero-cross timing of the P signal can be detected even when the data pattern of I or Q signal makes it impossible to detect the zero-cross timing from I and Q signal. Because the zero-cross timing of the P signal has a variation less than that of the zero-cross timing determined from I or Q signal, it is becomes possible to reproduce stable clock signals and in turn reliability of data demodulation can be improved.
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Invention: DQPSK delay detection circuit that produces stable clock signal in response to both I and Q signals