DMA controller with split channel transfer capability and FIFO buffering allowing transmit channel to get ahead of corresponding receive channel by preselected number of elements

Year	Description
1998	Invention patented by Natarajan Seshan, Jeffrey R. Quay, Kenneth L. Williams, and Michael J. Moody on April 2nd, 1998. Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices. DMA 143 allows for local variability of transfer rates in a split channel mode of operation by allowing a transmit channel to get ahead of a corresponding receive channel by a preselected number of data words.
Source: selected by the editor from original sources.

Invention: DMA controller with split channel transfer capability and FIFO buffering allowing transmit channel to get ahead of corresponding receive channel by preselected number of elements