DDR DRAM data coherence scheme

Year	Description
1999	Invention patented by Der-Min Yuan and Gyh-Bin Wang on December 1st, 1999. Abstract: In this invention a double data rate (DDR) DRAM is read and written with data coherence. The data is in the form of a data burst either interleaved or sequential and of any length. The data is read from the DDR DRAM depending on whether the starting address is even or odd and taking into consideration CAS latency. Both edges of the clock are used to transfer data in and out of the DDR DRAM. To write data only the starting address of the data burst is used to maintain data coherence. Data coherence is assured by a write followed by a read of the same data to and from the same memory cell.
Source: selected by the editor from original sources.

Invention: DDR DRAM data coherence scheme