DC application circuit with suppressed DC magnetization

Year	Description
1995	Invention patented by Kazuhiro Umeda and Syuzi Ichikawa on May 8th, 1995. Abstract: To a current mirror circuit or a voltage regulator are coupled a primary winding of a transformer (T.sub.3 or T.sub.4) or a choke coil (L.sub.2 or L.sub.3). Transistors (Q.sub.1 or Q.sub.2) making up a current mirror circuit or the voltage regulator are alternatingly bypassed by a bypass circuit constituted of a capacitor (C.sub.2) and other elements. A DC magnetization which may be otherwise caused in a core or a yoke of the transformer (T.sub.3) or the choke coil (L.sub.2) is canceled by allowing direct currents to flow in opposite directions to each other through the primary winding of the transformer (T.sub.4) or through the choke coil (L.sub.2). Alternatively, the DC magnetization which may be otherwise caused in the core or the yoke of the transformer (T.sub.4) or the choke coil (L.sub.3) is significantly suppressed by restricting the direct currents flowing through the primary winding of the transformer (T.sub.4) or the choke coil (L.sub.3). This results in no necessity to provide a gap in a magnetic circuit, ensuring the reduction in size of the entire circuit configuration including the transformer (T.sub.3) as well as improved characteristics.
Source: selected by the editor from original sources.

Invention: DC application circuit with suppressed DC magnetization