D/A converter with high jitter resistance

Year	Description
2003	Invention patented by Yasuo Morimoto, Toshio Kumamoto, and Takashi Okuda on April 7th, 2003. Abstract: A D/A converter including a plurality of potential generating sections. They each receive a 1-bit signal from one of an input terminal and delay circuit, and a clock signal or inverted clock signal from an input section or inverter for inverting the clock signal. When the clock signal or inverted clock signal is at a first signal level, they generate a first reference potential or second reference potential in response to the signal level of the 1-bit signal. When the clock signal or inverted clock signal is at the second level, they generate an intermediate potential between the first and second reference potentials. The potentials generated by the plurality of potential generating sections are combined by a combining section. The D/A converter can improve resistance to jitter, and to simplify the configuration of a post-stage filter circuit.
Source: selected by the editor from original sources.

Invention: D/A converter with high jitter resistance