Cube wireability enhancement with chip-to-chip alignment and thickness control

Year	Description
1995	Invention patented by Claude L. Bertin, John E. Cronin, and David J. Perlman on January 19th, 1995. Abstract: Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
Source: selected by the editor from original sources.

Invention: Cube wireability enhancement with chip-to-chip alignment and thickness control