CSP stacking technology using rigid/flex construction

Year	Description
2000	Invention patented by Andrew C. Ross on March 23th, 2000. Abstract: A stackable integrated circuit chip package comprising an interconnect sub-assembly which includes an interconnect substrate having first, second and third conductive pad arrays disposed thereon. The interconnect sub-assembly also includes a first rail member which is attached to the interconnect substrate and has a fourth conductive pad array disposed thereon, and a second rail member which is also attached to the interconnect substrate and has a fifth conductive pad array disposed thereon. The fourth and fifth conductive pad arrays are electrically connected to respective ones of the second and third conductive pad arrays of the interconnect substrate. In addition to the interconnect sub-assembly, the chip package of the present invention includes an integrated circuit chip which is electrically connected to the first conductive pad array of the interconnect substrate of the interconnect sub-assembly.
Source: selected by the editor from original sources.

Invention: CSP stacking technology using rigid/flex construction