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| Domain | Definition |
Computing | CPU 1. central processing unit. 2. Occasionally used (although less and less) to refer to the system unit. (2000-08-10). Source: The Free On-line Dictionary of Computing. |
Census | (Central Processing Unit) The unit of a computing system that includes the circuit controlling the interpretation and execution of instructions. (references) |
Source: compiled by the editor from various references; see credits. | |
(From Wikipedia, the free Encyclopedia)
The central processing unit (CPU) is the part of a computer that interprets and carries out the instructions contained in the software. In most CPUs, this task is divided between a control unit that directs program flow and one or more execution units that perform operations on data. Almost always, a collection of registers is included to hold operands and intermediate results.
The term CPU is often used vaguely to include other centrally important parts of a computer such as caches and input/output controllers, especially in computers with modern microprocessor chips that include several of these functions in one physical integrated circuit.
Manufacturers and retailers of desktop computers often erroneously describe the computer case and its contents as the CPU which is misleading.
A family of CPU designs is often referred to as a CPU architecture.
Notable CPU architectures include:
Emerging new CPU architectures include:
- Intel's x86 architecture
- Zilog's architecture
- IBM's System/360 architecture
- DEC's PDP-11 architecture, and its successor, the VAX architecture
- Motorola's 68000 architecture
- Sun Microsystems's SPARC architecture
- MIPS Computer Systems Inc's MIPS architecture
- HP's PA-RISC architecture
- DEC's Alpha architecture
- The AIM Alliance's PowerPC architecture
- DEC and Acorn ARM's StrongARM architecture
- SuperH's SuperH architecture
- UNIVAC 1100/2200 series architecture (currently supported by Unisys ClearPath IX computers)
- 1750A, the U.S.'s military standard computer.
- AP-101, the space shuttle's computer
Historically important CPUs have been:
- Intel's Itanium architecture
- AMD's x86-64 architecture
The above processor architectures could also be characterized by their CPU design like register size. Today most desktop computers have 32-bit processors; 64-bit processors are being phased in. Smaller devices like mobile phones, PDAs, or portable video game devices may have 16 or 8-bit processors.
- EDSAC- the first stored-program computer
- Apollo Guidance Computer, used in the moon flights
See also
- arithmetic and logical unit
- BIOS
- computer engineering
- CPU design
- CPU locking
- CPU power consumption
- floating point unit
- front side bus
- microcode
- motherboard
Source: adapted by the editor from Wikipedia, the free encyclopedia under a copyleft GNU Free Documentation License (GFDL) from the article "Central processing unit."
(From Wikipedia, the free Encyclopedia)
To a large extent, the design of a CPU, or central processing unit, is the design of its control unit. The modern (ie, 1965 to 1985) way to design control logic is to write a microprogramCPU design was originally an ad-hoc process. Just getting a CPU to work was a substantial governmental and technical event.
Key design innovations include cache, virtual memory, instruction pipelining, superscalar, CISC, RISC, virtual machine, emulators, microprogram, and stack.
General Purpose CPU Design
1950s: Early Designs
Computers throughout the early 1950s were similar in that they all contained a central processor that was unique to that machine. Programs written for one machine would not run on another, and most often wouldn't run on other machines from the same company. Each design differed in the types of instructions they supported, and few machines could be considered "general purpose". There simply wasn't enough space to wire in a full set of instructions using the technology of the day (for instance the SAGE systems filled entire floors) so each machine targeted a certain solution.
By the end of the 1950s commercial builders had developed factory-constructed, truck-deliverable computers. The most widely installed computer was the IBM 650, which used drum memory onto which programs were loaded using either paper tape or punch cards. Some very high-end machines also included core memory which provided higher speeds. Hard disks were also starting to become popular.
Computers are automatic abaci. The type of number system affects the way they work. In the early 1950s most computers were built for specific numerical processing tasks, and many machines used decimal numbers as their basic number system – that is, the mathematical functions of the machines worked in base-10 instead of base-2 as is common today. These were not merely binary coded decimal. The machines actually had ten vacuum tubes per digit in each register. Some early Soviet computer designers implemented systems based on ternary logic; that is, a bit could have three states: +1, 0, or -1, corresponding to positive, no, or negative voltage.
An early project for the U.S. Air Force, BINAC attempted to make a lightweight, simple computer by using binary arithmetic. It deeply impressed the industry.
As late as 1970, major computer languages such as "C" were unable to standardize their numeric behavior because decimal computers had groups of users too large to alienate.
Even when designers used a binary system, they still had many odd ideas. Some used sign-magnitude arthmetic (-1 = 10001), rather than modern two's complement arithmetic (-1 = 11111). Most computers used six-bit character sets, because they adequately encoded Hollerith cards. It was a major revelation to designers of this period to realize that the data word should be a multiple of the character size. They began to design computers with 12, 24 and 36 bit data words.
In this era, Grosch's law dominated computer design: Computer capacity increased as the square of its cost.
1960s: The Computer Revolution and CISC
One major problem with early computers was that a program for one would not work on others. Computer companies found that their customers had little reason to remain loyal to a particular brand, as the next computer they purchased would be incompatible anyway. At that point price and performance were usually the only concerns.
In 1962, IBM bet the company on a new way to design computers. The plan was to make an entire family of computers that could all run the same software, but with different performances, and at different prices. As users' requirements grew they could move up to larger computers, and still keep all of their investment in programs, data and storage media.
In order to do this they designed a single reference computer called the System 360 (or S/360). The System 360 was a virtual computer, a reference instruction set and capabilities that all machines in the family would support. In order to provide different classes of machines, each computer in the family would use more or less hardware emulation, and more or less microprogram emulation, to create a machine capable of running the entire System 360 instruction set.
For instance a low-end machine could include a very simple processor for low cost. However this would require the use of a larger microcode emulator to provide the rest of the instruction set, which would slow it down. A high-end machine would use a much more complex processor that could directly process more of the System 360 design, thus running a much simpler and faster emulator.
IBM chose to make the reference instruction set quite complex, and very capable. This was a conscious choice. Even though the computer was complex, its "control store" containing the microprogram would stay relatively small, and could be made with very fast memory. Another important effect was that a single instruction could describe quite a complex sequence of operations. Thus the computers would generally have to fetch fewer instructions from the main memory, which could be made slower, smaller and less expensive for a given combination of speed and price.
An often-overlooked feature of the S/360 was that it was the first instruction set designed for data processing, rather than mathematical calculation. The instruction set was designed to manipulate not just simple integer numbers, but text, scientific floating-point (similar to the numbers used in a calculator), and the decimal arithmetic needed by accounting systems.
The S/360 system was the first computer to make major use of binary coded decimal.
Almost all following computers included these innovations in some form. This basic set of features is called a "complex instruction set computer," or CISC (pronounced "sisk").
In many CISCs, an instruction could access either registers or memory, usually in several different ways. This made the CISCs easier to program, because a programmer could remember just thirty to a hundred instructions, and a set of three to ten "addressing modes," rather than thousands of distinct instructions. This was called an "orthogonal instruction set." The PDP-11 and Motorola 68000 architecture are examples of nearly orthogonal instruction sets.
1970s: Large Scale Integration
In the 1960s, the apollo guidance computer and minuteman missile made the integrated circuit economical and practical.
Around 1971, the first calculator and clock chips began to show that very small computers might be possible. The first microprocessor was the 4004, designed in 1971 for a calculator company, and produced by Intel. The 4004 is the direct ancestor of the Intel 80386, even now maintaining some code compatibility. Just a few years later, the word size of the 4004 was doubled to form the 8008.
By the mid-1970s, the use of integrated circuits in computers was commonplace. The whole decade consists of unheavals caused by the shrinking price of transistors.
It became possible to put an entire CPU on a single printed circuit board. The result was that minicomputers, usually with 16-bit words, and 4k to 64K of memory, came to be commonplace.
CISCs were believed to be the most powerful types of computers, because their microcode was small and could be stored in very high-speed memory.
Custom CISCs were constructed using "bit slice" computer logic such as the AMD 2900 chips, with custom microcode. A bit slice component is a piece of an ALU, register file or microsequencer. Most bit-slice integrated circuits were 4-bits wide.
By the late 1970s, the PDP-11 was developed, arguably the most advanced small computer of its day. Almost immediately, 32-bit CISCs were introduced, VAX and PDP-10.
Also, to control a cruise missile, Intel developed a more-capable version of its 8008 microprocessor, the 8080.
IBM continued to make large, fast computers. However the definition of large and fast now meant more than a megabyte of RAM, clock speeds near a hundred megahertz, and tens of megabytes of disk drives.
IBM's System 370 was a version of the 360 tweaked to run virtual computing environments. The virtual computer was developed in order to reduce the possibility of an unrecoverable software failure.
The Burroughs B300 series reached its largest market share. It was a stack computer programmed in a dialect of Algol. It used 64-bit fixed-point arithmetic, rather than floating-point.
All these different developments competed madly for marketshare.
Early 1980s: The Lessons of RISC
In the early 1980s, researchers at UC Berkeley and IBM both discovered that most computer languages produced only a small subset of the instructions of a CISC. Much of the power of the CPU was simply being ignored in real-world use. They realized that by making the computer simpler, less orthogonal, they could make it faster and less expensive at the same time.
At the same time CPUs were growing faster in relation to the memory they addressed. Designers also experimented with using large sets of internal registers. The idea was to cache intermediate results in the registers under the control of the compiler. This also reduced the number of addressing modes and orthogonality.
The computer designs based on this theory were called Reduced Instruction Set Computers, or RISC. RISCs generally had larger numbers of registers, accessed by simpler instructions, with a few instructions specifically to load and store data to memory. The result was a very simple core CPU running at very high speed, supporting the exact sorts of operations the compilers were using anyway.
One downside to the RISC design has been that the programs that run on them tend to be larger. That's because compilers have to generate longer sequences of the simpler instructions to accomplish the same results. Since these instructions need to be loaded from memory anyway, the larger code size offsets some of the RISC design's fast memory handling.
Recently, engineers have found ways to compress the reduced instruction sets so they fit in even smaller memory systems than CISCs. Examples of such compression schemes include the ARM's "Thumb" instruction set. In applications that do not need to run older binary software, compressed RISCs are coming to dominate sales.
Another approach to RISCs was the "niladic" or "zero-address" instruction set. This approach realized that the majority of space in an instruction was to identify the operands of the instruction. These machines placed the operands on a push-down (last-in, first out) stack. The instruction set was supplemented with a few instructions to fetch and store memory. Most used simple caching to provide extremely fast RISC machines, with very compact code. Another benefit was that the interrupt latencies were extremely small, smaller than most CISC machines (a rare trait in RISC machines). The first zero-address computer was developed by Charles Moore, placed six 5-bit instructions in a 32-bit word, and was a precursor to VLIW design (see below: 1990 to Today).
Commercial variants were mostly characterized as "FORTH" machines, and probably failed because that language became unpopular. Also, the machines were developed by defense contractors at exactly the time that the cold war ended. Loss of funding may have broken up the development teams before the companies could perform adequate commercial marketing.
RISC chips now dominate the market for 32-bit embedded systems. Smaller RISC chips are even becoming common in the cost-sensitive 8-bit embedded-system market. The main market for RISC CPUs has been systems that require low power or small size.
Even some CISC processors (based on architectures that were created before RISC became dominant) translate instructions internally into a RISC-like instruction set. These CISC chips include newer x86 and VAX models.
These numbers may surprise many, because the "market" is perceived to be desktop computers. However desktop computers are only a tiny fraction of the computers now sold. Most people own more computers in their car and house than on their desks. With Intel designs dominating the vast majority of all desktop sales, RISC is found only in the Apple computer lines.
Mid 1980s to Today: Synthesis
In the mid-to-late 1980s, designers began using a technique known as instruction pipelining, in which the processor works on multiple instructions in different stages of completion. For example, the processor may be retrieving the operands for the next instruction while calculating the result of the current one. Modern CPUs may use over a dozen such stages.
A similar idea, introduced only a few years later, was to execute multiple instructions in parallel on separate arithmetic-logic units (ALUs). Instead of operating on only one instruction at a time, the CPU will look for several similar instructions that are not dependent on each other, and run them all at the same time. The results are then interleaved when they exit, making it look like a single CPU was running (say) twice as fast while still using only one bus.
This approach, referred to as scalar processor design, is limited by the degree of instruction level parallelism (ILP), the number of non-dependent instructions in the program code. Some programs are able to run very well on scalar processors, notably graphics. However more general problems require complex logic, and this almost always results in instructions whose results are based on other results -- thus making them unable to run in parallelized forms.
Branching is one major culprit. For eample, the program might add two numbers and branch to a different code segment if the number is bigger than a third number. In this case even if the branch operation is sent to the second ALU for processing, it still must wait for the results from the addition. It thus runs no faster than if there were only one ALU.
To get around this limit, so-called superscalar designs were developed. Additional logic in the CPU looks at the code as it is being sent into the CPU, and "forces" it to be parallel. In the branching case a number of solutions are applied, including loking at past examples of the branch to see which one is most common (called branch prediction), and simply running that case as if there was no branch at all. A similar concept is speculative execution, where both sides of a branch are run at the same time, and the results of one or the other are thrown out once the answer is known.
These advances, which were originally developed from research for RISC-style designs, allow modern CISC processors to execute twelve or more instructions per clock cycle, when traditional CISC designs could take twelve or more cycles to execute just one instruction.
The resulting microcode is complex and error-prone, mostly due to the dependencies between different instructions. Furthermore, the electronics to coordinate these ALUs require more transistors, increasing power consumption and heat. In this respect RISC is superior because the instructions have less interdependence and make superscalar implementations easier. However, as Intel has demonstrated, the concepts can be applied to a CISC design, given enough time and money.
- Historical note: Most of these techniques (pipelining, branch prediction, etc.) were originally developed in the late 1950s by IBM on their Stretch mainframe computer.
1990 to Today: Looking Forward
The microcode that makes a superscalar processor is just-- computer code. In the early 1990s, a significant innovation was to realize that the coordination of a multiple-ALU computer could be moved into the compiler, the software that translates a programmer's instructions into machine-level instructions.
This type of computer is called a very long instruction word (VLIW) computer.
Parallelizing the code in the compiler has many practical advantages over doing so in the CPU.
Oddly, speed is not one of them. With enough transistors, the CPU could do everything at once. However all all those transistors make the chip larger, and therefore more expensive. The transistors also use power, which means that they generate heat that must be removed. The heat also makes the design less reliable.
Since compiling happens only once on the developer's machine, the control logic is "canned" in the final realization of the program. This means that it consumes no transistors, and no power, and therefore is free, and generates no heat.
The resulting CPU is simpler, and runs at least as fast as if the prediction were in the CPU.
There were several unsuccessful attempts to commercialize VLIW. The basic problem is that a VLIW computer does not scale to different price and performance points, as a microprogrammed computer can.
Also, VLIW computers maximize throughput, not latency, so they were not attractive to the engineers designing controllers and other computers embedded in machinery. The embedded systems markets had often pioneered other computer improvements by providing a large market that did not care about copatibility with older software.
In January 2000, a company called Transmeta took the interesting step of placing a compiler in the central processing unit, and making the compiler translate from a reference byte code (in their case, x86 instructions) to an internal VLIW instruction set. This approach combines the hardware simplicity, low power and speed of VLIW RISC with the compact main memory system and software reverse-compatibility provided by popular CISC.
Later this year (2002), Intel intends to release a chip based on what they call an Explicitly Parallel Instruction Computer (EPIC) design. This design supposedly provides the VLIW advantage of increased instruction throughput. However, it avoids some of the issues of scaling and complexity, by explicitly providing in each "bundle" of instructions information concerning their dependencies. This information is calculated by the compiler, as it would be in a VLIW design. The early versions will also be reverse-compatible with current x86 software by means of an on-chip emulation mode.
Also, we may soon see multi-threaded CPUs. Current designs work best when the computer is running only a single program, however nearly all modern operating systems allow the user to run multiple programs at the same time. For the CPU to change over and do work on another program requires an expensive context-switch. In contrast, a multi-threaded CPU could handle instructions from multiple programs at once.
To do this, such CPU's include several sets of registers. When a context switch occurs the contents of the "working registers" are simply copied into one of a set of registers for this purpose.
Such designs often include thousands of registers instead of hundreds as in a typical design. On the downside, registers tend to be somewhat expensive in chip space needed to implement them. This chip space might otherwise be used for some other purpose.
Another track of development is to combine reconfigurable logic with a general-purpose CPU. In this scheme, a special computer language compiles fast-running subroutines into a bit-mask to configure the logic. Slower, or less-critical parts of the program can be run by sharing their time on the CPU. This process has the capability to create devices such as software radios, by using digital signal processing to perform functions usually performed by analog electronics.
As the lines between hardware and software increasingly blur due to progress in design methodology and availability of chips such as FPGAs and cheaper production processes, even open-source hardware has begun to appear. Loosely-knit communities like OpenCores have recently announced completely open CPU architectures such as the OpenRISC which can be readily implemented on FPGAs or in custom produced chips, by anyone, without paying license fees.
Embedded Design
The majority of computer systems in use today are embedded in other machinery, such as telephones, clocks, appliances, vehicles, and infrastructure. These "embedded systems" usually have small requirements for memory, modest program sizes, and often simple but unusual input/output systems. For example, most embedded systems lack keyboards, screens, disks, printers, or other recognizable I/O devices of a personal computer. They may control electric motors, relays or voltages, and read switches, variable resistors or other electronic devices. Often, the only I/O device readable by a human is a single light-emitting diode, and severe cost or power constraints can even eliminate that.
In contrast to general-purpose computers, embedded systems often seek to minimize interrupt latency over instruction throughput.
For example, low-latency CPUs generally have relatively few registers in their central processing units. When an electronic device causes an interrupt, the intermediate results, the registers, have to be saved before the software responsible for handling the interrupt can run, and then must be put back after it is finished. If there are more registers, this saving and restoring process takes more time, increasing the latency.
Other design issues
Another common problem involves virtual memory. Historically, random-access memory has been thousands of times more expensive than rotating mechanical storage. For businesses, and many general computing tasks, it is a good compromise to never let the computer run out of memory, an event which would halt the program, and greatly inconvenience the user.
Instead of halting the program, many computer systems save less-frequently used blocks of memory to the rotating mechanical storage. In essence, the mechanical storage becomes main memory. However, mechanical storage is thousands of times slower than electronic memory.
Thus, almost all general-purpose computing systems use "virtual memory" and also have unpredictable interrupt latencies.
A few operating system contain a real-time scheduler. Such a scheduler keeps critical pieces of code and data in solid-state RAM and guarantees a minimum amount of CPU time and a maximum interrupt latency.
One interesting near-term possibility would be to eliminate the bus. Modern vertical laser diodes enable this change. In theory, an optical computer's components could directly connect through a holographic or phased open-air switching system. This would provide a large increase in effective speed and design flexibility, and a large reduction in cost. Since a computer's connectors are also its most likely failure point, a busless system might be more reliable, as well.
Another farther-term possibility is to use light instead of electricity for the digital logic itself. In theory, this could run about 30% faster and use less power, as well as permit a direct interface with quantum computational devices. The chief problem with this approach is that for the foreseeable future, electronic devices are faster, smaller (i.e. cheaper) and more reliable. An important theoretical problem is that electronic computational elements are already smaller than some wavelengths of light, and therefore even wave-guide based optical logic may be uneconomic compared to electronic logic. We can therefore expect the majority of development to focus on electronics, no matter how unfair it might seem. See also optical computing.
Yet another possibility is the "clockless CPU." Unlike conventional processors, this processor has no central clock to coordinate the progress of data through the pipeline; instead, this unit coordinates stages of the CPU using logic devices called "pipline controls" or "FIFO sequencers." Basically, the pipline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. The advantage is that components can run at different speeds in the clockless CPU. In a clocked CPU, no component can run faster than the clock rate.
See also
- Microprocessor
- Moore's Law
- Amdahls Law
- Simultaneous multithreading
Source: adapted by the editor from Wikipedia, the free encyclopedia under a copyleft GNU Free Documentation License (GFDL) from the article "CPU design."
(From Wikipedia, the free Encyclopedia)
Modern personal computer CPUs (central processing units) consume a considerable amount of electrical power. This must be considered when choosing a power supply unit, and when power consumption is constrained by production and cost.CPUs in other electronics often use far less power. For example, the CPUs in mobile phones or pacemakers use just a few microwatts. CPUs in personal computers use a lot of power because the manufacturers are rewarded for raw speed instead of energy efficiency. This top-performance speed requires significantly more power in the cases of most (but not all) CPU architectures. One of the simplest way to reduce the power consumption of a PC's CPU is just to slow its clock rate.
CPUs for desktop computers typically use more power than any other component inside the computer. The steady trend in CPU power supplies over the past decade has been towards using lower voltages and having considerably higher currents. While energy-saving features have been instituted in PCs for when they are idle, the overall consumption of today's high-drain CPUs is considerable. This is in strong contrast with the much lower energy consumption of CPUs designed for low-power environments. One such CPU, the Intel XScale, can run at 600 MHz with only half a watt of power, whereas x86 PC processors from Intel in the same performance bracket consume roughly eighty times as much energy.
Processor manufacturers usually release two power consumption numbers for a CPU, first is the 'typical' thermal power, which is how much power the CPU draws under normal load, and the other is the maximum thermal power, which is how much power it can draw if you give it a worst-case set of instructions. As an example, the Pentium 4 2.8GHz has a typical thermal power of 68.4 W, but a maximum thermal power of 85 W. When the CPU is idle, it will draw far less than the typical thermal power. Manufactureres generally don't release the idle thermal power for desktop chips.
External links
- http://pub40.ezboard.com/f3dxtremeamdforum.showMessage?topicID=176.topic
- http://www6.tomshardware.com/howto/20021021/powersupplies-02.html
- http://www.experts-exchange.com/Hardware/Desktops/Q_20424890.html
- http://pcxtrem.free.fr/guides/watts.php3
- http://www.amd-hardware.com/Watts.htm
- http://www.aceshardware.com/read.jsp?id=55000279
- Processor electrical specifications
Source: adapted by the editor from Wikipedia, the free encyclopedia under a copyleft GNU Free Documentation License (GFDL) from the article "CPU electrical consumption."
(From Wikipedia, the free Encyclopedia)
The Motorola 68000 is a CISC microprocessor, the first member of a successful family of microprocessors, which were all mostly software compatible. The entire series was often referred to as the m68k, or simply 68k
The 68000 family
People who are familiar with the PDP-11 or VAX usually feel comfortable with the 68000. With the exception of the split of general purpose registers into specialized data and address registers, the 68000 architechture is in many ways a 32-bit PDP-11.
- Motorola 68EC000
- Motorola 68HC000
- Motorola 68008
- Motorola 68010
- Motorola 68012
- Motorola 68020
- Motorola 68EC020
- Motorola 68030
- Motorola 68EC030
- Motorola 68040
- Motorola 68EC040
- Motorola 68LC040
- Motorola 68060
- Motorola CPU32 (aka Motorola 68330)
- Motorola Coldfire
- Motorola Dragonball
History
Originally, the MC68000 was designed for use in household products (at least, that is what an internal memo from Motorola claimed). Luckily it was used for the design of homecomputers like the Amiga and Atari. It was also used in the Sega Genesis/MegaDrive, NeoGeo and several Arcade Machines as their main CPU. In the Sega Saturn, the 68000 was used as the sound processor, and in the Atari Jaguar they were used as a main controller for all the other dedicated hardware IC's.
Notable design wins include the Amiga, the Apple Macintosh, and the original Sun Microsystems and SGI UNIX machines. 68000 derivatives persisted in the UNIX market for many years, because the architecture so strongly resembles the Digital PDP-11 and VAX, and is an excellent computer for running C code. The 68000 eventually saw its greatest success as a controller. Thousands of HP, Printronix and Adobe printers used it. Its derivative microcontrollers, the CPU32 and Coldfire processors have been manufactured in the millions as automotive engine controllers. It also sees use by medical manufacturers and many printer manufacturers because of its low cost, convenience, and good stability. As of 2001, the Dragonball versions of the processor are used in the popular Palm series of PDAs from Palm Computing and Handspring's Visor, though the architecture is being phased out in favor of the ARM processor core.
The Voyage 200 PLT
The Motorola 68000 is also used in Texas Instruments' latest line of calculators. These four calculators (the TI-89, TI-92, TI-92 Plus, and Voyage 200 PLT) are the highest-end calculators. The TI-92 had a 10 MHz processor and 68KB RAM, and was released in 1995. It was upgraded to the TI-92 Plus (in 1998) with 188KB RAM, 384KB Flash ROM, and the same 10 MHz processor. Also released in that year was the TI-89, identical except it was in a more traditionally shaped case. Around 2000, the TI-92 Plus and the TI-89 were upgraded to Hardware Version 2, and gaines a 12 MHz processor and a few other hidden upgrades. In 2002, Texas Instruments relaeased its latest über-calculator: the Voyage 200 PLT. This had the Hardware Version 2 12MHz processor, 188 KB RAM, and a whopping 3.7 MB Flash ROM. It also had a clock and an Apps Desktop, both of which were summarily released as Flash ROM updates for the TI-92 Plus and TI-89.
Initial samples of the 68000 were released in 1982, and competed against the Intel 8086 and Intel 80286 with some success. Initial clock rates were a then-blisteringly fast 8MHz, with a rather slow eight to ten clocks per instruction. However, the instructions did more than Intel processors. Motorola ceased production of the 68000 in 2000, although derivatives, notably the CPU32 family, continue in production. As of 2001, Hitachi continued to manufacture the 68000 under license.
Architecture
Address bus
The 68000 was a clever compromise. When the 68000 was introduced, 16-bit busses were really the most practical size. However, the 68000 was designed with 32-bit registers and address spaces, on the assumption that hardware prices would fall. To address the perceived markets, the actual 68000 was designed in three forms. The base-form had a 24-bit address, and a 16-bit data bus. The short form, the 68008, had an 18-bit address (possibly 19 or 20 bits, at least one firm addressed 512KBytes with 68008s), and an 8-bit data bus. A planned future form (later the 68020) had a 32-bit data and address bus.
Internal registers
The CPU had 8 general-purpose data registers (D0-D7), and 8 address registers (A0-A7). The last address register was also the standard stack pointer, and could be called either A7 or SP. This was a good number of registers in many ways. It was small enough to make the 68000 respond quickly to interrupts (because only 15 or 16 had to be saved), and yet large enough to make most calculations fast.
Having two types of registers was mildly annoying at times, but really not hard to use in practice. Reportedly, it allowed the CPU designers to achieve a higher degree of parallelism, by using an auxiliary execution unit for the address registers.
Status register
The 68000 comparison, arithmetic and logic operations set bits in a status register to record their results for use by later conditional jumps. The bits were "Z"ero, "C"arry, e"X"tend, and "N"egative. The eXtend bit deserves special mention, because it was separated from the Carry. This permitted the extra bit from arithmetic, logic and shift operations to be separated from the carry for flow-of-control and linkage.
The instruction set
The designers attempted to make the assembly language orthogonal. That is, instructions were divided into operations and address modes. Almost all address modes were available for almost all instructions. Many programmers disliked the "near" orthogonality, while others were grateful for the attempt.
At the bit level, the person writing the assembler would clearly see that these "instructions" could become any of several different op-codes. It was quite a good compromise because it gave almost the same convenience as a truly orthogonal machine, and yet also gave the CPU designers freedom to fill in the op-code table.
The minimal instruction size was huge for its day at 16 bits. Furthermore, many instructions and addressing modes added extra words on the back for addresses, more address-mode bits, etc.
Many designers believed that the M68000 architecture had compact code for its cost, especially when produced by compilers. This belief in more compact code led to many of its design wins, and much of its longevity as an architecture.
Most embedded system designers are acutely aware of the costs of memory.
This belief (or feature, depending on the designer) continued to make design wins for the instruction set (with updated CPUs) up until the ARM architecture introduced compressed Thumb op-codes that were more compact.
Privilege levels
The CPU, and later the whole family, implemented exactly two levels of privilege. User mode gave access to everything except the interrupt level control. Supervisor privilege gave access to everything. An interrupt always became supervisory. The supervisor bit was stored in the status register, and visible to user programs.
A real advantage of this system was that the supervisor level had a separate stack pointer. This permitted a multitasking system to use very small stacks for tasks, because the designers did not have to allocate the memory required to hold the stack frames of a maximum stack-up of interrupts.
Interrupts
The CPU recognized 8 interrupt levels. Levels 0 through 7 were strictly prioritized. That is, a higher-numbered interrupt could always interrupt a lower-numbered interrupt. In the status register, a privileged instruction allowed one to set the current minimum interrupt level, blocking lower priority interrupts. Level 7 was not maskable. Level 0 could be interrupted by any higher level. The level was stored in the status register, and was visible to user-level programs.
The "exception table" (interrupt vector addresses) was fixed at addresses 0 through 1023, permitting 256 32-bit vectors. The first vector was the starting stack address, and the second was the starting code address. Vectors 3..15 were used to report various errors: bus error, address error, illegal instruction, zero division, CH1 & CHK2 vector, privilige violation, and some reserved vectors that became line 1010 emulator, line 1111 emulator, and hardware breakpoint. Vector 24 started the real interrupts: spurious interrupt (i.e. it wasn't properly hand-shaken), and level 1 .. level 7 autovectors, then the 15 TRAP vectors, then some more reserved vectors, then the user defined vectors.
The interrupt controller was originally a separate IC, the 68901. This chip performed a rather complicated dance on the bus to translate the seven pull-down interrupt lines into vectored interrupts (level 1 through 7). The 68901 also provided a basic UART and (if memory serves) a periodic interrupt timer. The Motorola 68901 had a number of severe defects, including the ability to lose the highest-priority interrupt if it and the clock interrupt happened within some window of each other. The Mostek part was superior.
The fixed exception table was screamingly annoying for hardware designers.
One wants a ROM bootstrap, but then once the OS is up, one wants installable vectors.
A lot of effort went into circumventing the fixed vectors, either through trampolines (tables addressed to RAM) in ROM or through bank-switchable memory.
Another problem was the "privilege" logic. The designers had clearly planned on having a minimal, but adequate, two-tiered security system to support something like a UNIX kernel. This would limit the ability of user programs to access hardware and interrupts. The design had security holes, which were fixed in later processor models.
The 68000 was also unable to correctly return from an exception on a failing memory access, a crucial feature to enable true virtual memory. To simulate unlimited RAM, one wants to interrupt when a memory access fails, and then the interrupt routine will allocate a block of real RAM and read a piece of data on disk into it. Several companies did succeed in making 68000 based Unix workstations with virtual memory that worked, by using two 68000 chips running in parallel on different phased clocks. When the "leading" 68000 encountered a bad memory access, extra hardware would interrupt the "main" 68000 to prevent it from also encountering the bad memory access. This interrupt routine would handle the virtual memory functions and restart the "leading" 68000 in the correct state to continue properly synchronized operation when the "main" 68000 returned from the interrupt. Obviously this is an expensive, tricky, and very inconvenient technique, and they upgraded to the 68010 as quickly as possible.
A more subtle problem was that the 68000 could not easily run a virtual image of itself without simulating a large number of instructions. This problem persists in many modern versions of the architecture, which is rarely used in these applications. This lack caused the later versions of the Intel 80386 to win designs in avionic control, where software reliability was achieved by executing software virtual machines.
In the next major revision, the 68010, most of these problems were fixed.
Instruction set details
The standard address modes were:
Plus: access to the status register, and, in later models, other special registers.
- Register direct
- data register, e.g. "D0"
- address register, e.g. "A6"
- Register indirect
- Simple address, e.g. (A0)
- Address with post-increment, e.g. (A0)+
- Address with pre-decrement, e.g. -(A0)
- Address with a 16-bit signed offset, e.g. 16(A0)
- Note that the actual increment or decrement size was dependent on the operand request: a byte read instruction incremented the address register by 1, a word read by 2, and a long read by 4.
- Register indirect with an Index
- 8-bit signed offset, e.g. 8(A0, D0) or 8(A0, A1)
- PC (program counter) relative with displacement
- 16-bit signed offset, e.g. 16(PC). This mode was very useful.
- 8-bit signed offset with index, e.g. 8(PC, D2)
- Absolute memory location
- Either a numer, e.g. "$4000", or a symbolic name translated by the assembler
- Most 68000 assemblers used the "$" symbol for hexadecimal, instead of "0x".
- Immediate mode
- Stored in the instruction, e.g. "#400".
Most instructions had dot-letter suffixes, permitting operations to occur on 8-bit bytes (".b"), 16-bit words (".w"), and 32-bit longs (".l").
Most instructions are dyadic, that is, the operation has a source, and a destination, and the destination is changed. Notable instructions were:
- Arithmetic: ADD, SUB, MULU (unsigned multiply), MULS (signed multiply), DIVU, DIVS, NEG (additive negation), and CMP (a sort of subtract that set the status bits, but did not store the result)
- Binary Coded Decimal Arithmetic: ABCD, and SBCD
- Logic: EOR (exclusive or), AND, NOT (logical not)
- Shifting: (logical, i.e. right shifts put zero in the most significant bit) LSL, LSR, (arithmetic shifts, i.e. sign-extend the most significant bit) ASR, ASL, (Rotates through eXtend and not:) ROXL, ROXR, ROL, ROR
- Bit manipulation in memory: BSET (to 1), BCLR (to 0), and BTST (set the Zero bit)
- Multiprocessing control: TAS, test-and-set, performed an indivisible bus operation, permitting semaphores to be used to synchronize several processors sharing a single memory
- Flow of control: JMP (jump), JSR (jump to subroutine), BSR (relative address jump to subroutine), RTS (return from subroutine), RTE (return from exception, i.e. an interrupt), TRAP (trigger a software exception similar to software interrupt), (CHK a conditional software exception)
- Decision: Bcc (a branch where the "cc" specified one of 16 tests of the condition codes in the status register: equal, greater than, less-than, cary, and most combinations and logical inversions, available form the status register).
Source: adapted by the editor from Wikipedia, the free encyclopedia under a copyleft GNU Free Documentation License (GFDL) from the article "Motorola 68000."
| The following table is compiled from various sources, across various languages. When English abbreviations or acronyms come from a non-English source, this is noted. | |||
| Entry | Source | Expression | Field |
CPU | English | Mainframe | N/A |
CPU | French | Convention Postale Universelle | Law, Post & Telecom |
Source: compiled by the editor, based on several corpora (additional references). | |||
| Context | Synonyms within Context (source: adapted from Roget's Thesaurus). |
Intellect | Central processing unit, CPU; arithmetic and logical unit, ALU. |
| Source: adapted from Roget's Thesaurus. | |
Crosswords: CPU |
| English words defined with "CPU": C.P.U., central processing unit, central processor, CISC, complex instruction set computer, complex instruction set computing, computer peripheral, core dump ♦ mainframe, memory, memory board ♦ peripheral, peripheral device, processor ♦ storage, store. (references) |
| Specialty definitions using "CPU": CPU Info Center, CPU time, CPU Wars. (references) |
| Domain | Title | ||
Books |
| ||
Periodicals |
| ||
Theater & Movies | |||
Music |
| ||
High Tech |
| ||
Source: compiled by the editor from various references; see credits. | |||
 |  |
| "Inside computers 6" by Marcio Simioni Commentary: "Well, I needed some photos like this to use in an ad and it was really difficult to find. So, if someone needs it now, won't have to open the cpu." | "The insides" by Rene Cerney Commentary: "My old parts - AMD 1.3 Gigahertz CPU and a 32 MB stick of PC 133 RAM." |
Source: photographs selected by the editor, with permission from the photographers. | |
| Subject | Topic | Quote |
Business | Also in strong demand are low cost and high performance multimedia PCs featuring multimedia functions such as high-speed CPU, CD-ROM drives, DVD, fax modems, audio speakers providing various sound effects including 3D, microphones for voice input, hard disk drives, and multiple sets of pre-installed packaged software (e.g., 20-30 applications). (references) | |
Benefiting from leading-edge technology and applications developed for the Internet and related information technologies, U.S. imports are forecast to increase annually by 12 percent in real terms through 2003. U.S. PC manufacturers are strong competitors as a result of high performance semiconductor CPU design and embedded software technology that offers competitive or superior performance at frequently lower costs than Japanese manufacturers can provide. (references) | ||
Source: compiled by the editor from ICON Group International, Inc.; see credits. | ||
| "CPU" is generally used as a noun (singular) -- approximately 80.85% of the time. "CPU" is used about 141 times out of a sample of 100 million words spoken or written in English. Its rank is based on over 700,000 words used in the English language. Some parts-of-speech are not covered due to the samples used by the British National Corpus. (note: percents less than one-hundredth of one percent have been omitted) |
| Parts of Speech | Percent | Usage per 100 Million Words | Rank in English |
| Noun (singular) | 80.85% | 114 | 30,294 |
| Noun (proper) | 10.64% | 15 | 90,616 |
| Noun (common) | 8.51% | 12 | 101,599 |
| Total | 100.00% | 141 | N/A |
Source: compiled by the editor from several corpora; see credits.
Expressions using "CPU": cpu board ♦ cpu Info Center ♦ cpu time ♦ cpu Wars. Additional references. | |
| Hyphenated Usage | |
Beginning with "CPU": cpu-independent, cpu-intensive, cpu-specific. | |
Ending with "CPU": dual-cpu, four-cpu. | |
| Source: compiled by the editor from various references; see credits. | |
| The following statistics estimate the number of searches per day across the major English-language search engines as identified by various trade publications. Hyperlinks lead to commercial use of the expression at Amazon.com. |
| Expression | Frequency per Day | Expression | Frequency per Day |
cpu | 2,073 | cpu temperature monitor | 78 |
cpu fan | 336 | cpu cooling fan | 73 |
cpu test | 247 | motherboard cpu combo | 68 |
cpu temperature | 214 | cpu overclocking | 66 |
intel cpu | 211 | pentium 4 cpu | 53 |
cpu cooler | 199 | cpu fsb | 50 |
cpu upgrade | 178 | cpu killer | 49 |
cpu idle | 156 | cpu overclock | 48 |
cpu speed | 148 | cpu temp monitor | 45 |
amd cpu | 144 | cpu holder | 44 |
cpu cooling | 142 | cpu case | 44 |
cpu id | 119 | cpu comparison | 43 |
cpu motherboard | 106 | cpu processor | 43 |
cpu benchmark | 105 | dual cpu motherboard | 40 |
cpu s | 97 | water cooling cpu | 37 |
cpu z | 97 | cpu review | 33 |
cpu temp | 97 | motherboard cpu combos | 33 |
cpu speed test | 93 | 100 cpu usage | 32 |
cpu monitor | 90 | cpu stand | 32 |
cpu cool | 85 | cpu magazine | 32 |
cpu usage | 32 | ||
| Source: compiled by the editor from various references; see credits. | |||
| Language | Translations for "CPU"; alternative meanings/domain in parentheses. | |
Chinese | 中心处理装置. (various references) | |
Hebrew | יחידת עבוד מרכזית. (various references) | |
Korean | 중앙 처리 장치. (various references) | |
Pig Latin | ucpay.(various references) | |
Portuguese | unidade central de processamento (central processing unit). (various references) | |
Serbo-Croatian | central processing unit, mikroprocesor (microprocessor). (various references) | |
| Source: compiled by the editor from various translation references. | ||
Scrabble® Enable2K-Verified Anagrams | |
Direct Anagrams: cup. | |
| Words within the letters "c-p-u" | |
-1 letter: up. | |
| Words containing the letters "c-p-u" | |
+1 letter: coup, cups, cusp, puce, puck, scup. | |
+2 letters: caput, chump, clump, coupe, coups, coypu, croup, crump, culpa, cupel, cupid, cuppa, cuppy, cusps, cutup, picul, pluck, pouch, pubic, puces, pucka, pucks, pudic, punch, scaup, sculp, scups, uncap. | |
+3 letters: apercu, backup, campus, capful, carpus, catsup, chumps, clumps, clumpy, cockup, copout, copula, corpus, couped, coupes, couple, coupon, coypou, coypus, croupe, croups, croupy, crumps, culpae, cupels, cupful, cupids, cupola, cuppas, cupped, cupper, cupric, cuprum, cupula, cupule, cusped, cuspid, cuspis, cutups, cyprus, eggcup, eyecup, faceup, hiccup, hubcap, kickup, lockup, mockup, mudcap, occupy, oilcup, paunch, pickup, piculs, plucks, plucky, pouchy, pounce, precut, public, pucker, pumice, punchy, putsch, recoup, scaups, sculps, sculpt, spruce, sprucy, teacup, uncaps, unclip, unpack, unpick, upcast, upcoil, upcurl, uptick. | |
| Source: compiled by the editor from various references; see credits. SCRABBLE® is a registered trademark. All intellectual property rights in and to the game are owned in the U.S.A and Canada by Hasbro Inc., and throughout the rest of the world by J.W. Spear & Sons Limited of Maidenhead, Berkshire, England, a subsidiary of Mattel Inc. Mattel and Spear are not affiliated with Hasbro. | |
| 1. Crosswords 2. Usage: Commercial 3. Images: Slideshow 4. Images: Digital Art | 5. Quotations: Non-fiction 6. Usage Frequency 7. Expressions 8. Expressions: Internet | 9. Translations: Modern 10. Abbreviations 11. Acronyms 12. Anagrams | 13. Bibliography |
Copyright © Philip M. Parker, INSEAD. Terms of Use.
