CPLD scalable and array architecture

  

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CPLD scalable and array architecture

Invention: CPLD scalable and array architecture

Year    Description
2001Invention patented by Shi-dong Zhou on February 14th, 2001. Abstract: A scalable pterm generator provides enhanced programming flexibility in logic devices such as PLAs. A scalable pterm generator includes both wide AND logic and alternative OR logic that enables efficient implementation of functions not requiring the full wide AND logic. According to an embodiment of the invention, a scalable pterm generator comprises a wide AND gate, an alternative logic circuit, and an output control circuit. The alternative logic circuit includes OR logic, thereby providing an alternative to the pure AND functionality of the wide AND gate. A set of logic input lines connects to both the inputs of the wide AND gate and the inputs of the alternative logic circuit. An output control circuit selects the final output of the scalable pterm generator. According to an embodiment of the invention, the output control circuit comprises a programmable circuit. According to another embodiment of the invention, the output control circuit comprises a multiplexer. According to another embodiment of the invention, the wide AND logic is carried out in stages by a plurality of smaller AND gates. An OR gate taps into the outputs of one of the stages to provide the alternative logic. The wide AND logic can be divided into multiple stages, with OR gates provided at each stage. An output control circuit selects from the OR and wide AND outputs to provide the final output of the scalable pterm generator.
Source: selected by the editor from original sources.

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