CG-WL voltage boosting scheme for twin MONOS

Year	Description
2002	Invention patented by Nori Ogura and Seki Ogura on July 7th, 2002. Abstract: This invention provides a circuit and a method for providing an override voltage to control gates through boosting of a selected word line for TWIN metal oxide, nitride semiconductor MONOS memory. The boosted voltages are required to program, erase and read the 2-bit MONOS memory cell in this invention. This invention relates to providing a means of using capacitive coupling between selected word lines and neighboring control gates to boost the voltage for the program, erase and write modes of MONOS memory. Capacitive coupling to boost the voltage on the control gates adjacent to the selected word lines is used instead of generating the required boosted voltage through the control gate and bit line decoders and drivers. This voltage boosting method saves address decoder silicon area, decoder circuit complexity, reduces address decode set-up time, and eliminates the need for extra voltage supplies for address decoders.
Source: selected by the editor from original sources.

Invention: CG-WL voltage boosting scheme for twin MONOS