Avalanche programmed floating gate memory cell structure with program element in polysilicon

Year	Description
1998	Invention patented by Stewart G. Logie on December 27th, 1998. Abstract: A non-volatile memory cell structure comprises a floating gate, a reverse breakdown injection element at least partially formed in a polysilicon layer and operatively coupled to the floating gate, and a transistor at least partially formed in a region of a semiconductor substrate, operatively coupled to the floating gate. In a further aspect, a control gate is capacitively coupled to the floating gate and is formed in said polysilicon layer. The reverse breakdown electron injection element comprises a first, second, and third active regions, the first and second regions comprising a first p/n junction, the second and third active regions comprising a second p/n junction.
Source: selected by the editor from original sources.

Invention: Avalanche programmed floating gate memory cell structure with program element in polysilicon