At-speed built-in self testing of multi-port compact sRAMs

Year	Description
1999	Invention patented by Yuejian Y. Wu and Liviu Calin on September 22th, 1999. Abstract: A built-in self test (BIST) for a multi-port compact sRAM (CsRAM) uses a BIST controller which operates at the speed of the system, while the CsRAM is tested at the memory speed. The circuitry for testing allows multiple random accesses of the CsRAM per system clock cycle. In this way, timing-related defects in the CsRAM can be detected. The CsRAM is virtually partitioned into "k" sections, the sections being tested simultaneously from different ports with identical and complementary test data. A conventional (BIST) controller can be used with minimal addition of hardware in a collar arranged around the memory array.
Source: selected by the editor from original sources.

Invention: At-speed built-in self testing of multi-port compact sRAMs