Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle

Year	Description
1998	Invention patented by James A. Farrell and Bruce A. Gieseke on June 1st, 1998. Abstract: An arbiter system for the instruction issue logic of a CPU has at least two encoder circuits that select instructions in an instruction queue for issue to first and second execution units, respectively, based upon the positions of the instructions within the queue and requests by the instructions for the first and/or second execution units. As a result, since the instruction can request different execution units, this system is compatible with architectures where the execution units may have different capabilities to execute different instructions, i.e., each integer execution unit may not be able to execute all of the instructions in the CPU's integer instruction set. According to the present invention, one of the encoder circuits is subordinate to the other circuit. The subordinate encoder circuit selects instructions from the instruction queue based not only on the positions of the instructions and their requests, but the instruction selection of the dominant encoder circuit.
Source: selected by the editor from original sources.

Invention: Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle