Copyright © Philip M. Parker, INSEAD. Terms of Use.
| Year | Description |
| 1995 | Invention patented by Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, David Christoph Kuchinski, Billy Jack Knowles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, and Vincent John Smoral on April 26th, 1995. Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory elements on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. The architecture uses all the pins for networking. Each chip has eight 16 bit processors, and eight respective 32K memories. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. The scalable chip has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. A fully distributed programmable router is provided by the processing memory elements that form a node. There is program compatibility for the fully scalable system. |
| Source: selected by the editor from original sources. | |
Copyright © Philip M. Parker, INSEAD. Terms of Use.
