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DMA ACCESS ARBITRATION DEVICE IN WHICH CPU CAN ARBITRATE ON BEHALF OF ATTACHMENT HAVING NO ARBITER
DMA ACCESS AUTHORIZATION FOR 64-BIT I/O ADAPTERS ON PCI BUS
DMA ADDRESS BUFFER AND CACHE-MEMORY CONTROL SYSTEM
DMA CACHE CONTROL LOGIC
DMA CELLULAR RADIO SYSTEM WITH A CHANNEL QUALITY CRITERION
DMA CHANNEL CONTROL APPARATUS CAPABLE OF ASSIGNING INDEPENDENT DMA TRANSFER CONTROL LINE TO RESPECTIVE EXPANSION SLOTS
DMA CHANNEL FOR HIGH-SPEED ASYNCHRONOUS DATA TRANSFER
DMA COMPUTER SYSTEM FOR DRIVING AN LCD DISPLAY IN A GPS RECEIVER
DMA CONFIGURABLE CHANNEL WITH MEMORY WIDTH N AND WITH STEERING LOGIC COMPRISING N MULTIPLEXORS, EACH MULTIPLEXOR HAVING A SINGLE ONE-BYTE INPUT AND N ONE-BYTE OUTPUTS
DMA CONFIGURABLE RECEIVE CHANNEL WITH MEMORY WIDTH N AND WITH STEERING LOGIC COMPRESSING N MULTIPLEXORS
DMA CONTROL APPARATUS FOR MULTI-BYTE SERIAL-BIT TRANSFER IN A PREDETERMINED BYTE PATTERN AND BETWEEN MEMORIES ASSOCIATED WITH DIFFERENT ASYNCHRONOUSLY OPERATING PROCESSORS FOR A DISTRIBUTED SYSTEM
DMA CONTROL DEVICE AND RECORDING APPARATUS HAVING PRIORITY CONTROL CIRCUIT DYNAMICALLY CHANGES DEFINED PRIORITIES WITHIN PREDETERMINED TIME INTERVAL
DMA CONTROL DEVICE CONTROLLING SEQUENTIAL STORAGE OF DATA
DMA CONTROL FOR CONTINUING TRANSFER TO INPUT/OUTPUT DEVICE IN A CYCLE STEAL MODE
DMA CONTROL SYSTEM ENABLING FLYBY TRANSFER TO SYNCHRONOUS MEMORY
DMA CONTROLLER
DMA CONTROLLER ADAPTED FOR TRANSFERRING DATA IN TWO-DIMENSIONAL MAPPED ADDRESS SPACE
DMA CONTROLLER AND COHERENCY-TRACKING UNIT FOR EFFICIENT DATA TRANSFERS BETWEEN COHERENT AND NON-COHERENT MEMORY SPACES
DMA CONTROLLER ARRANGEMENT HAVING PLURALITY OF DMA CONTROLLERS AND BUFFER POOL HAVING PLURALITY OF BUFFERS ACCESSIBLE TO EACH OF THE CHANNELS OF THE CONTROLLERS
DMA CONTROLLER COMPRISING BUS SWITCHING MEANS FOR CONNECTING DATA BUS SIGNALS WITH OTHER DATA BUS SIGNALS WITHOUT PROCESS OR INTERVENTION
DMA CONTROLLER FOR DMA TRANSFERRING IMAGE DATA FOR ONE PAGE WITHOUT INCREASING A BURDEN ON A CPU
DMA CONTROLLER FOR MEMORY SCRUBBING
DMA CONTROLLER HAVING A PLURALITY OF DMA CHANNELS EACH HAVING MULTIPLE REGISTER SETS STORING DIFFERENT INFORMATION CONTROLLING RESPECTIVE DATA TRANSFER
DMA CONTROLLER HAVING JUMP FUNCTION
DMA CONTROLLER HAVING MULTIPLE CHANNELS AND BUFFER POOL HAVING PLURALITY OF BUFFERS ACCESSIBLE TO EACH CHANNEL FOR BUFFERING DATA TRANSFERRED TO AND FROM HOST COMPUTER
DMA CONTROLLER HAVING PROGRAMMABLE LOGIC ARRAY FOR OUTPUTTING CONTROL INFORMATION REQUIRED DURING A NEXT TRANSFER CYCLE DURING ONE TRANSFER CYCLE
DMA CONTROLLER IN WHICH BUS ACCESS RATIO CAN BE SET
DMA CONTROLLER INCLUDING A FIFO REGISTER AND A RESIDUAL REGISTER FOR DATA BUFFERING AND HAVING DIFFERENT OPERATING MODES
DMA CONTROLLER MAILING AUTO-INITIALIZE HALTING UNIT
DMA CONTROLLER OF A RAID STORAGE CONTROLLER WITH INTEGRATED XOR PARITY COMPUTATION CAPABILITY ADAPTED TO COMPUTE PARITY IN PARALLEL WITH THE TRANSFER OF DATA SEGMENTS
DMA CONTROLLER PERFORMING DATA TRANSFER BY 2-BUS CYCLE TRANSFER MANNER
DMA CONTROLLER RESPONSIVE TO TRANSITION OF A REQUEST SIGNAL BETWEEN FIRST STATE AND SECOND STATE AND MAINTAINING OF SECOND STATE FOR CONTROLLING DATA TRANSFER
DMA CONTROLLER TRANSLATES VIRTUAL I/O DEVICE ADDRESS RECEIVED DIRECTLY FROM APPLICATION PROGRAM COMMAND TO PHYSICAL I/O DEVICE ADDRESS OF I/O DEVICE ON DEVICE BUS
DMA CONTROLLER USING A PREDETERMINED NUMBER OF TRANSFERS PER REQUEST
DMA CONTROLLER USING A PROGRAMMABLE TIMER, A TRANSFER COUNTER AND AN OR LOGIC GATE TO CONTROL DATA TRANSFER INTERRUPTS
DMA CONTROLLER WHICH CAN BE CONTROLLED BY HOST AND LOCAL PROCESSORS
DMA CONTROLLER WHICH OPTIMIZES TRANSFER RATE OF DATA AND METHOD THEREFOR
DMA CONTROLLER WHICH PROVIDES MULTIPLE CHANNELS
DMA CONTROLLER WHICH RECEIVES SIZE DATA FOR EACH DMA CHANNEL
DMA CONTROLLER WHICH RELEASES BUSES TO EXTERNAL DEVICES WITHOUT RELINQUISHING THE BUS UTILITY RIGHT
DMA CONTROLLER WITH CHANNEL TAGGING
DMA CONTROLLER WITH DYNAMICALLY VARIABLE ACCESS PRIORITY
DMA CONTROLLER WITH MECHANISM FOR CONDITIONAL ACTION UNDER CONTROL OF STATUS REGISTER, PRESPECIFIED PARAMETERS, AND CONDITION FIELD OF CHANNEL COMMAND
DMA CONTROLLER WITH PREFETCH CACHE RECHECKING IN RESPONSE TO MEMORY FETCH DECISION UNIT'S INSTRUCTION WHEN ADDRESS COMPARING UNIT DETERMINES INPUT ADDRESS AND PREFETCH ADDRESS COINCIDE
DMA CONTROLLER WITH RESPONSE MESSAGE AND RECEIVE FRAME ACTION TABLES
DMA CONTROLLER WITH SEMAPHORE COMMUNICATION PROTOCOL
DMA CONTROLLER WITH SPLIT CHANNEL TRANSFER CAPABILITY AND FIFO BUFFERING ALLOWING TRANSMIT CHANNEL TO GET AHEAD OF CORRESPONDING RECEIVE CHANNEL BY PRESELECTED NUMBER OF ELEMENTS
DMA DATA PATH ALIGNER AND NETWORK ADAPTOR UTILIZING SAME
DMA DATA STREAMING
DMA DATA TRANSFER APPARATUS, MOTION PICTURE DECODING APPARATUS USING THE SAME, AND DMA DATA TRANSFER METHOD
DMA DEVICE WITH LOCAL PAGE TABLE
DMA DOORBELL
DMA DRIVEN PROCESSOR CACHE
DMA EMULATION FOR NON-DMA CAPABLE INTERFACE CARDS
DMA EMULATION VIA INTERRUPT MUXING
DMA EXCLUSIVE CACHE STATE PROVIDING A FULLY PIPELINED INPUT/OUTPUT DMA WRITE MECHANISM
DMA HANDSHAKE PROTOCOL
DMA OPERABLE IN COMPLIANCE WITH POINTERS, EACH INCLUDING A DISCRIMINATION BIT
DMA SYSTEM FOR RE-ARBITRATING MEMORY ACCESS PRIORITY DURING DMA TRANSMISSION WHEN AN ADDITIONAL REQUEST IS RECEIVED
DMA TRANSFER DEVICE
DMA TRANSFER DEVICE CAPABLE OF HIGH-SPEED CONSECUTIVE ACCESS TO PAGES IN A MEMORY
DMA TRANSFER FROM A STORAGE UNIT TO A HOST USING AT LEAST TWO TRANSFER RATES AND CYCLIC ERROR DETECTION
DMA TRANSFER METHOD FOR A SYSTEM INCLUDING A SINGLE-CHIP PROCESSOR WITH A PROCESSING CORE AND A DEVICE INTERFACE IN DIFFERENT CLOCK DOMAINS
DMA TRANSFER OF AN INTERLEAVED STREAM
DMA WITH DYNAMICALLY ASSIGNED CHANNELS, FLEXIBLE BLOCK BOUNDARY NOTIFICATION AND RECORDING, TYPE CODE CHECKING AND UPDATING, COMMANDS, AND STATUS REPORTING
DMA-TRANSFERRING STREAM DATA APPARATUS BETWEEN A MEMORY AND PORTS WHERE A COMMAND LIST INCLUDES SIZE AND START ADDRESS OF DATA STORED IN THE MEMORY
DMC COMPLEX CATALYST AND PROCESS FOR ITS PREPARATION
DMD ARCHITECTURE AND TIMING FOR USE IN A PULSE WIDTH MODULATED DISPLAY SYSTEM
DMD ARCHITECTURE AND TIMING FOR USE IN A PULSE-WIDTH MODULATED DISPLAY SYSTEM
DMD ARCHITECTURE TO IMPROVE HORIZONTAL RESOLUTION
DMD DISPLAY SYSTEM
DMD DISPLAY SYSTEM CONTROLLER
DMD ILLUMINATION COUPLER
DMD MODULATED CONTINUOUS WAVE LIGHT SOURCE FOR IMAGING SYSTEMS
DMD MODULATED CONTINUOUS WAVE LIGHT SOURCE FOR XEROGRAPHIC PRINTER
DMD SCANNER
DMD-BASED PROJECTOR FOR INSTITUTIONAL USE
DME SYSTEM WITH BROADCASTING FUNCTION
DMNPE CAGED NUCLEIC ACID AND VECTOR
DMOS ARCHITECTURE USING LOW N-SOURCE DOSE CO-DRIVEN WITH P-BODY IMPLANT COMPATIBLE WITH E.SUP.2 PROM CORE PROCESS
DMOS DEVICE STRUCTURE, AND RELATED MANUFACTURING PROCESS
DMOS FABRICATION PROCESS IMPLEMENTED WITH REDUCED NUMBER OF MASKS
DMOS FIELD EFFECT TRANSISTOR WITH IMPROVED ELECTRICAL CHARACTERISTICS AND METHOD FOR MANUFACTURING THE SAME
DMOS POWER TRANSISTOR WITH REDUCED NUMBER OF CONTACTS USING INTEGRATED BODY-SOURCE CONNECTIONS
DMOS POWER TRANSISTORS WITH REDUCED NUMBER OF CONTACTS USING INTEGRATED BODY-SOURCE CONNECTIONS
DMOS PROCESS MODULE APPLICABLE TO AN E.SUP.2 CMOS CORE PROCESS
DMOS TRANSISTOR HAVING A HIGH RELIABILITY AND A METHOD FOR FABRICATING THE SAME
DMOS TRANSISTOR PROTECTED AGAINST "SNAP-BACK"
DMOS TRANSISTOR PROTECTED AGAINST POLARITY REVERSAL
DMOS TRANSISTOR STRUCTURE HAVING IMPROVED PERFORMANCE
DMOS TRANSISTOR STRUCTURE WITH GATE ELECTRODE TRENCH FOR HIGH DENSITY INTEGRATION AND METHOD OF FABRICATING THE STRUCTURE
DMOS TRANSISTOR WITH LOW ON-RESISTANCE AND METHOD OF FABRICATION
DMOS TRANSISTORS HAVING TRENCHED GATE OXIDE
DMOS TRANSISTORS WITH DIFFUSION MERGED BODY REGIONS MANUFACTURED WITH REDUCED NUMBER OF MASKS AND ENHANCED RUGGEDNESS
DMOS TRANSISTORS WITH SCHOTTKY DIODE BODY STRUCTURE
DMOST JUNCTION BREAKDOWN ENHANCEMENT
DMPO SPIN TRAPPING COMPOSITIONS AND METHODS OF USE THEREOF
DMS DETECTING AGENT, METHOD FOR PREPARING THE SAME AND DMS DETECTOR TUBE
DMSO/BASE HYDROLYSIS METHOD FOR THE DISPOSAL OF HIGH EXPLOSIVES AND RELATED ENERGETIC MATERIALS
DMT TEST METHOD FOR DETERMINING ADSL CAPABILITY OF CABLES
DMT TIME-DOMAIN EQUALIZER ALGORITHM
DMT-TIC DI- AND TRI-PEPTIDE DERIVATIVES AND RELATED COMPOSITIONS AND METHODS OF USE |
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