Copyright © Philip M. Parker, INSEAD. Terms of Use.
CM TYPE DIRECTIONAL COUPLER
CM-CHITIN DERIVATIVES AND USE THEREOF
CMA PRODUCTION UTILIZING ACETATE ION EXCHANGE FROM FERMENTATION BROTH
CMA PRODUCTION UTILIZING ORGANIC ION EXCHANGE FROM FERMENTATION BROTH
CMA-BASED ANTENNA SYSTEM
CMC JOINT SPLINT
CMG CONTROL BASED ON ANGULAR MOMENTUM TO CONTROL SATELLITE ATTITUDE
CMI ENCODER CIRCUIT
CMI SIGNAL TIMING RECOVERY
CMI-CODE CODING METHOD, CMI-CODE DECODING METHOD, CMI CODING CIRCUIT, AND CMI DECODING CIRCUIT
CMIS CIRCUIT AND ITS DRIVER
CMIS DEVICE WITH INCREASED GAIN
CML THERAPY
CML-CMOS CONVERSION CIRCUIT
CMOS 3.3 VOLT OUTPUT BUFFER WITH 5 VOLT PROTECTION
CMOS ACTIVE PIXEL CELL WITH SELF RESET FOR IMPROVED DYNAMIC RANGE
CMOS ACTIVE PIXEL FOR IMPROVING SENSITIVITY
CMOS ACTIVE PIXEL IMAGE SENSOR WITH EXTENDED DYNAMIC RANGE AND SENSITIVITY
CMOS ACTIVE PIXEL SENSOR
CMOS ACTIVE PIXEL SENSOR HAVING IN-PIXEL LOCAL EXPOSURE CONTROL
CMOS ACTIVE PIXEL SENSOR TYPE IMAGING SYSTEM ON A CHIP
CMOS ACTIVE PIXEL SENSOR USING A PINNED PHOTO DIODE
CMOS ACTIVE PIXEL SENSOR USING NATIVE TRANSISTORS
CMOS ACTIVE PIXEL WITH MEMORY FOR IMAGING SENSORS
CMOS ACTIVE PIXEL WITH RESET NOISE REDUCTION
CMOS ACTIVE PIXEL WITH SCAVENGING DIODE
CMOS ADJUSTABLE BANDGAP REFERENCE WITH LOW POWER AND LOW VOLTAGE PERFORMANCE
CMOS AMPLIFIER CIRCUIT AND CCD DELAY LINE WITH CMOS AMPLIFIER
CMOS AMPLIFIER FOR OPTOELECTRONIC RECEIVERS
CMOS AMPLIFIER PROVIDING AUTOMATIC OFFSET CANCELLATION
CMOS AMPLIFIER WITH OFFSET ADAPTATION
CMOS AMPLIFIERS WITH MULTIPLE GAIN SETTING CONTROL
CMOS ANALOG FRONT END ARCHITECTURE WITH VARIABLE GAIN FOR DIGITAL CAMERAS AND CAMCORDERS
CMOS ANALOG SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF
CMOS ANALOG-TO-DIGITAL CONVERTER AND TEMPERATURE SENSING DEVICE USING THE SAME
CMOS AND ECL LOGIC CIRCUIT REQUIRING NO INTERFACE CIRCUITRY
CMOS APPARATUS FOR DRIVING TRANSMISSION LINES
CMOS ASSISTED OUTPUT STAGE
CMOS BAND GAP REFERENCE CIRCUIT
CMOS BANDGAP VOLTAGE AND CURRENT REFERENCES
CMOS BANDGAP VOLTAGE REFERENCE
CMOS BI-DIRECTIONAL CURRENT MODE DIFFERENTIAL LINK WITH PRECOMPENSATION
CMOS BI-DIRECTIONAL DIFFERENTIAL LINK
CMOS BIDIRECTIONAL BUFFER FOR MIXED VOLTAGE APPLICATIONS
CMOS BIDIRECTIONAL BUFFER WITHOUT ENABLE CONTROL SIGNAL
CMOS BIDIRECTIONAL TRANSCEIVER/TRANSLATOR OPERATING BETWEEN TWO POWER SUPPLIES OF DIFFERENT VOLTAGES
CMOS BOOSTING CIRCUIT UTILIZING FERROELECTRIC CAPACITORS
CMOS BOOTSTRAPPED OUTPUT DRIVER METHOD AND CIRCUIT
CMOS BTL COMPATIBLE BUS AND TRANSMISSION LINE DRIVER
CMOS BUFFER AMPLIFIER
CMOS BUFFER CIRCUIT
CMOS BUFFER CIRCUIT HAVING INCREASED SPEED
CMOS BUFFER CIRCUIT HAVING POWER-DOWN FEATURE
CMOS BUFFER CIRCUIT WHICH IS NOT INFLUENCED BY BOUNCE NOISE
CMOS BUFFER CIRCUIT WITH CONTROLLED CURRENT SOURCE
CMOS BUFFER FOR DRIVING A LARGE CAPACITIVE LOAD
CMOS BUFFER HAVING OUTPUT TERMINAL OVERVOLTAGE-CAUSED LATCH-UP PROTECTION
CMOS BUFFER HAVING STABLE THRESHOLD VOLTAGE
CMOS BUFFER WITH CONTROLLED SLEW RATE
CMOS BUS AND TRANSMISSION LINE DRIVER HAVING COMPENSATED EDGE RATE CONTROL
CMOS BUS AND TRANSMISSION LINE DRIVER HAVING PROGRAMMABLE EDGE RATE CONTROL
CMOS BUS DRIVER CIRCUIT
CMOS BUS DRIVER CIRCUIT WITH IMPROVED SPEED
CMOS CELL AND CIRCUIT DESIGN FOR IMPROVED IDDQ TESTING
CMOS CHEMICAL BATH PURIFICATION
CMOS CHIP TO CHIP SETTABLE INTERFACE RECEIVER CELL
CMOS CIRCUIT
CMOS CIRCUIT COMPOSED OF CMOS CIRCUIT BLOCKS ARRANGED IN BIT-PARALLEL DATA PATHS
CMOS CIRCUIT FOR AVERAGING DIGITAL-TO-ANALOG CONVERTERS
CMOS CIRCUIT FOR GENERATING A CURRENT REFERENCE, THE CIRCUIT COMPRISING A TRANSISTOR IN A WEAK INVERSION REGION
CMOS CIRCUIT FOR GENERATING VOLTAGE RELATED TO TRANSISTOR GATE LENGTH
CMOS CIRCUIT FOR IMPLEMENTING BOOLEAN FUNCTIONS
CMOS CIRCUIT FOR IMPROVED POWER-ON RESET TIMING
CMOS CIRCUIT FOR MAINTAINING A CONSTANT SLEW RATE
CMOS CIRCUIT FOR PROVIDING A BANDCAP REFERENCE VOLTAGE
CMOS CIRCUIT FOR RECEIVING ECL SIGNALS
CMOS CIRCUIT OF GAAS/GE ON SI SUBSTRATE
CMOS CIRCUIT PROVIDING 90 DEGREE PHASE DELAY
CMOS CIRCUIT TECHNIQUE FOR IMPROVED SWITCHING SPEED OF SINGLE-ENDED AND DIFFERENTIAL DYNAMIC LOGIC
CMOS CIRCUIT WITH ALL-AROUND DIELECTRICALLY INSULATED SOURCE-DRAIN REGIONS
CMOS CIRCUIT WITH CROWBAR LIMITING FUNCTION
CMOS CIRCUIT WITH INCREASED BREAKDOWN STRENGTH
CMOS CIRCUIT WITH REDUCED SIGNAL SWING
CMOS CIRCUITRY WITH SHORTENED P-CHANNEL LENGTH ON ULTRATHIN SILICON ON INSULATOR
CMOS CLASS AB AMPLIFIER FOR DRIVING CAPACITIVE AND RESISTIVE LOADS
CMOS CLASS AB OPERATIONAL AMPLIFIER OPERATING FROM A SINGLE 1.5V CELL
CMOS CLOCK DRIVERS WITH INDUCTIVE COUPLING
CMOS CLOCKED LOGIC DECODER
CMOS COLOR IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME
CMOS COMPARATOR
CMOS COMPARATOR OUTPUT CIRCUIT WITH HIGH GAIN AND HYSTERESIS
CMOS COMPARATOR WITH HYSTERESIS
CMOS COMPATABLE SURFACE MACHINED PRESSURE SENSOR AND METHOD OF FABRICATING THE SAME
CMOS COMPATIBLE BAND GAP REFERENCE
CMOS COMPATIBLE INTEGRATED PRESSURE SENSOR
CMOS COMPATIBLE PIXEL CELL THAT UTILIZES A GATED DIODE TO RESET THE CELL
CMOS COMPATIBLE PROCESS FOR MAKING A TUNABLE NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE
CMOS COMPATIBLE SINGLE PHASE CCD CHARGE TRANSFER DEVICE
CMOS COMPATIBLE SOI PROCESS
CMOS CONSTANT CURRENT REFERENCE CIRCUIT
CMOS CURRENT AMPLIFIER
CMOS CURRENT CONTROLLED DELAY ELEMENT USING CASCODED COMPLEMENTARY DIFFERENTIAL AMPLIFIERS WITH REPLICATED BIAS CLAMP
CMOS CURRENT CONVEVOR AND ITS FILTER APPLICATIONS
CMOS CURRENT MIRROR
CMOS CURRENT MIRROR WITH OFFSET ADAPTATION
CMOS CURRENT SOURCE CIRCUIT
CMOS CURRENT STEERING CIRCUIT
CMOS CURRENT-MODE FOUR-QUADRANT ANALOG MULTIPLIER
CMOS DAC WITH HIGH IMPEDANCE DIFFERENTIAL CURRENT DRIVERS
CMOS DELAY CIRCUIT
CMOS DELAY CIRCUIT WITH CONTROLLABLE DELAY
CMOS DELAY LINE HAVING DUTY CYCLE CONTROL
CMOS DEVICE
CMOS DEVICE AND CIRCUIT AND METHOD OF OPERATION DYNAMICALLY CONTROLLING THRESHOLD VOLTAGE
CMOS DEVICE AND METHOD FOR FABRICATING THE SAME
CMOS DEVICE AND METHOD FOR MANUFACTURING THE SAME
CMOS DEVICE AND METHOD OF MANUFACTURING THE SAME
CMOS DEVICE AND PROCESS
CMOS DEVICE CONNECTED TO AT LEAST THREE POWER SUPPLIES FOR PREVENTING LATCH-UP
CMOS DEVICE FOR USE IN CONNECTION WITH AN ACTIVE MATRIX PANEL
CMOS DEVICE HAVING A REDUCED SHORT CHANNEL EFFECT
CMOS DEVICE HAVING HIGH-DENSITY RESISTANCE ELEMENTS
CMOS DEVICE STRUCTURE WITH REDUCED RISK OF SALICIDE BRIDGING AND REDUCED RESISTANCE VIA USE OF A ULTRA SHALLOW, JUNCTION EXTENSION, ION IMPLANTATION
CMOS DEVICE STRUCTURE WITH REDUCED RISK OF SALICIDE BRIDGING AND REDUCED RESISTANCE VIA USE OF A ULTRA SHALLOW, JUNCTION EXTENSION, ION IMPLANTATION PROCESS
CMOS DEVICE STRUCTURE WITH REDUCED SHORT CHANNEL EFFECT AND MEMORY CAPACITOR
CMOS DEVICE STRUCTURES AND METHOD OF MAKING SAME
CMOS DEVICE USING ADDITIONAL IMPLANT REGIONS TO ENHANCE ESD PERFORMANCE AND DEVICE MANUFACTURED THEREBY
CMOS DEVICE WITH DEEP CURRENT PATH FOR ESD PROTECTION
CMOS DEVICE WITH IMPROVED WIRING DENSITY
CMOS DEVICE WITH PERPENDICULAR CHANNEL CURRENT DIRECTIONS
CMOS DEVICE WITH TRENCH STRUCTURE
CMOS DEVICES COMPRISING THIN FILM TRANSISTORS ARRANGED ON A SUBSTRATE
CMOS DEVICES HARDENED AGAINST TOTAL DOSE RADIATION EFFECTS
CMOS DEVICES HAVING MINIMIZED DRAIN CONTACT AREA
CMOS DEVICES WITH BALANCED DRIVE CURRENTS BASED ON SIGE
CMOS DIFFERENTIAL AMPLIFIER
CMOS DIFFERENTIAL AMPLIFIER FOR A DELTA SIGMA MODULATOR APPLICABLE FOR AN ANALOG-TO-DIGITAL CONVERTER
CMOS DIFFERENTIAL AMPLIFIER HAVING CONSTANT TRANSCONDUCTANCE AND SLEW RATE
CMOS DIFFERENTIAL AMPLIFIER HAVING OFFSET VOLTAGE CANCELLATION AND COMMON-MODE VOLTAGE CONTROL
CMOS DIFFERENTIAL DRIVER CIRCUIT FOR HIGH OFFSET GROUND
CMOS DIFFERENTIAL OPERATIONAL AMPLIFIER
CMOS DIFFERENTIAL TWISTED-PAIR DRIVER
CMOS DIFFERENTIAL VOLTAGE CONTROLLED LOGARITHMIC ATTENUATOR AND METHOD
CMOS DIGITAL CLOCK AND DATA RECOVERY CIRCUIT
CMOS DIGITAL LEVEL SHIFT CIRCUIT
CMOS DIGITAL OPTICAL NAVIGATION CHIP
CMOS DIGITAL TO ANALOG SIGNAL CONVERTER CIRCUIT
CMOS DIGITAL-CONTROLLED DELAY GATE
CMOS DISK DRIVE MOTOR CONTROL CIRCUIT HAVING BACK-EMF BLOCKING CIRCUITRY
CMOS DISK DRIVE MOTOR CONTROL CIRCUIT HAVING BACK-EMF REGULATOR CIRCUITRY
CMOS DRIVER
CMOS DRIVER AND ON-CHIP TERMINATION FOR GIGABAUD SPEED DATA COMMUNICATION
CMOS DRIVER CIRCUIT
CMOS DRIVER CIRCUIT FOR PROVIDING A LOGIC FUNCTION WHILE REDUCING PASS-THROUGH CURRENT
CMOS DRIVER CIRCUIT HAVING REDUCED SWITCHING NOISE
CMOS DRIVER FOR FAST SINGLE-ENDED BUS
CMOS DRIVER USING OUTPUT FEEDBACK PRE-DRIVE
CMOS DRIVER WHICH USES A HIGHER VOLTAGE TO COMPENSATE FOR THRESHOLD LOSS OF THE PULL-UP NFET
CMOS DUAL-STAGE DIFFERENTIAL RECEIVER-AMPLIFER
CMOS DYNAMIC LOGIC CIRCUITRY USING QUANTUM MECHANICAL TUNNELING STRUCTURES
CMOS DYNAMIC LOGIC STRUCTURE
CMOS DYNAMIC MEMORY DEVICE HAVING MULTIPLE FLIP-FLOP CIRCUITS SELECTIVELY COUPLED TO FORM SENSE AMPLIFIERS SPECIFIC TO NEIGHBORING DATA BIT LINES
CMOS DYNAMIC RAM WITH DISCRETE SENSE AMPLIFIERS AND A COMMON SENSE AMPLIFIER AND A METHOD FOR THE MANUFACTURE THEREOF
CMOS ECL INPUT BUFFER
CMOS ECL OUTPUT BUFFER
CMOS ECL/TTL OUTPUT CIRCUIT
CMOS EEPROM CELL WITH TUNNELING WINDOW IN THE READ PATH
CMOS ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH MINIMAL LOADING FOR HIGH SPEED CIRCUIT APPLICATIONS
CMOS ESD PROTECTION CIRCUIT WITH PARASITIC SCR STRUCTURES
CMOS ESD PROTECTION STRUCTURE
CMOS FABRICATION PROCESS WITH DIFFERENTIAL RAPID THERMAL ANNEAL SCHEME
CMOS FET WITH P-WELL WITH P- TYPE HALO UNDER DRAIN AND COUNTERDOPED N- HALO UNDER SOURCE REGION
CMOS FLASH ANALOG TO DIGITAL CONVERTER COMPENSATION
CMOS FLASH ANALOG-TO-DIGITAL CONVERTER WITH HYSTERESIS
CMOS FLIP-FLOP HAVING NON-VOLATILE STORAGE
CMOS FOLDING AMPLIFIER HAVING HIGH RESOLUTION AND LOW POWER CONSUMPTION
CMOS FOVEAL IMAGE SENSOR CHIP
CMOS FREQUENCY CONVERSION USING DUAL MIXERS FOR SIDEBAND SUPPRESSION
CMOS FREQUENCY SYNTHESIZER
CMOS FULL ADDER CIRCUIT WITH PAIR OF CARRY SIGNAL LINES
CMOS FULL DUPLEX TRANSMISSION-RECEPTION CIRCUIT
CMOS GAIN BOOSTING SCHEME USING POLE ISOLATION TECHNIQUE
CMOS GATE ARCHITECTURE FOR INTEGRATION OF SALICIDE PROCESS IN SUB 0.1 . .MUM DEVICES
CMOS GATE ARRAY CONFIGURED AS A SRAM WITH LOAD RESISTORS OVER GATE ELECTRODES
CMOS GATE ARRAY WITH VERTICAL TRANSISTORS
CMOS GATE ELECTRODE USING SELECTIVE GROWTH AND A FABRICATION METHOD THEREOF
CMOS GATE STACK
CMOS GAUGE DRIVER
CMOS GIGABIT SERIAL LINK DIFFERENTIAL TRANSMITTER AND RECEIVER
CMOS HIGH VOLTAGE DRIVE OUTPUT BUFFER
CMOS HIGH VOLTAGE SWITCH
CMOS HIGH-SPEED DIFFERENTIAL TO SINGLE-ENDED CONVERTER CIRCUIT
CMOS HIGH-TO-LOW VOLTAGE BUFFER
CMOS I/O CIRCUIT WITH 3.3 VOLT OUTPUT AND TOLERANCE OF 5 VOLT INPUT
CMOS I/O CIRCUIT WITH HIGH-VOLTAGE INPUT TOLERANCE
CMOS IC DEVICE SUPPRESSING SPIKE NOISE
CMOS IMAGE SENSOR
CMOS IMAGE SENSOR AND A FABRICATION METHOD FOR THE SAME
CMOS IMAGE SENSOR AND MANUFACTURING METHOD THEREOF
CMOS IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME
CMOS IMAGE SENSOR ARRAY HAVING CHARGE SPILLOVER PROTECTION FOR PHOTODIODES
CMOS IMAGE SENSOR BASED ON FOUR TRANSISTOR PHOTOCELL
CMOS IMAGE SENSOR CAPABLE OF INCREASING FILL FACTOR AND DRIVING METHOD THEREOF
CMOS IMAGE SENSOR CAPABLE OF INCREASING PUNCH-THROUGH VOLTAGE AND CHARGE INTEGRATION OF PHOTODIODE
CMOS IMAGE SENSOR CAPABLE OF INCREASING PUNCH-THROUGH VOLTAGE AND CHARGE INTEGRATION OF PHOTODIODE, AND METHOD FOR FORMING THE SAME
CMOS IMAGE SENSOR EMPLOYING SILICIDE EXCLUSION MASK TO REDUCE LEAKAGE AND IMPROVE PERFORMANCE
CMOS IMAGE SENSOR HAVING A CHOPPER-TYPE COMPARATOR TO PERFORM ANALOG CORRELATED DOUBLE SAMPLING
CMOS IMAGE SENSOR HAVING AUTOMATIC REFERENCE VOLTAGE CONTROLLER
CMOS IMAGE SENSOR HAVING COMMON OUTPUTTING TRANSISTORS AND METHOD FOR DRIVING THE SAME
CMOS IMAGE SENSOR HAVING ENHANCED PHOTOSENSITIVITY AND METHOD FOR FABRICATING THE SAME
CMOS IMAGE SENSOR INTEGRATED TOGETHER WITH MEMORY DEVICE
CMOS IMAGE SENSOR N-TYPE PIN-DIODE STRUCTURE
CMOS IMAGE SENSOR UNIT WITH SERIAL TRANSMITTING FUNCTION
CMOS IMAGE SENSOR WITH COMPLETE PIXEL RESET WITHOUT KTC NOISE GENERATION
CMOS IMAGE SENSOR WITH DIFFERENT PIXEL SIZES FOR DIFFERENT COLORS
CMOS IMAGE SENSOR WITH EQUIVALENT POTENTIAL DIODE
CMOS IMAGE SENSOR WITH EQUIVALENT POTENTIAL DIODE AND METHOD FOR FABRICATING THE SAME
CMOS IMAGE SENSOR WITH EXTENDED DYNAMIC RANGE
CMOS IMAGE SENSOR WITH HIGH QUANTUM EFFICIENCY
CMOS IMAGE SENSOR WITH IMPROVED FILL FACTOR
CMOS IMAGE SENSOR WITH ON-CHIP PATTERN RECOGNITION
CMOS IMAGE SENSOR WITH PIXEL LEVEL A/D CONVERSION
CMOS IMAGE SENSOR WITH PIXEL LEVEL GAIN CONTROL
CMOS IMAGE SENSOR WITH REDUCED FIXED PATTERN NOISE
CMOS IMAGE SENSOR WITH TESTING CIRCUIT FOR VERIFYING OPERATION THEREOF
CMOS IMAGER AND METHOD OF FORMATION
CMOS IMAGER CELL HAVING A BURIED CONTACT
CMOS IMAGER CELL HAVING A BURIED CONTACT AND METHOD OF FABRICATION
CMOS IMAGER COLUMN BUFFER GAIN COMPENSATION CIRCUIT
CMOS IMAGER HAVING ASYNCHRONOUS PIXEL READOUT IN ORDER OF PIXEL ILLUMINATION
CMOS IMAGER WITH A SELF-ALIGNED BURIED CONTACT
CMOS IMAGER WITH AN A/D PER PIXEL CONVERTOR
CMOS IMAGER WITH DISCHARGE PATH TO SUPPRESS RESET NOISE
CMOS IMAGER WITH IMPROVED SENSITIVITY
CMOS IMAGER WITH LIGHT SHIELD
CMOS IMAGER WITH SELECTIVELY SILICIDED GATES
CMOS IMAGER WITH STORAGE CAPACITOR
CMOS IMAGING DEVICE WITH INTEGRATED DEFECTIVE PIXEL CORRECTION CIRCUITRY
CMOS IMAGING DEVICE WITH INTEGRATED FLASH MEMORY IMAGE CORRECTION CIRCUITRY
CMOS IMAGING DEVICE WITH INTEGRATED IDENTIFICATION CIRCUITRY
CMOS IMPLEMENTED OUTPUT BUFFER CIRCUIT FOR PROVIDING ECL LEVEL SIGNALS
CMOS INPUT BUFFER PROTECTION CIRCUIT
CMOS INPUT BUFFER WITH HIGH SPEED AND LOW POWER
CMOS INPUT BUFFER WITH LOW POWER CONSUMPTION
CMOS INPUT BUFFER WITH NMOS GATE COUPLED TO V.SUB.SS THROUGH UNDOPED GATE POLY RESISTOR
CMOS INPUT BUFFER WITH NMOS GATE COUPLED TO VSS THROUGH UNDOPED GATE POLY RESISTOR
CMOS INPUT CIRCUIT
CMOS INPUT CIRCUIT FOR PROVIDING LOGICAL OUTPUT SIGNAL FROM TTL COMPATIBLE INPUT SIGNAL
CMOS INPUT CIRCUIT WITH IMPROVED SUPPLY VOLTAGE REJECTION | CMOS INPUT LEVEL-SHIFTING PAD
CMOS INPUT STAGE
CMOS INPUT STAGE WITH WIDE COMMON-MODE RANGE
CMOS INPUT VOLTAGE CLAMP
CMOS INPUT WITH TEMPERATURE AND V.SUB.CC COMPENSATED THRESHOLD
CMOS INPUT WITH VCC COMPENSATED DYNAMIC THRESHOLD
CMOS INPUT/OUTPUT CONTROL CIRCUIT CAPABLE OF TOLERATING DIFFERENT VOLTAGE INPUT
CMOS INTEGRATED CIRCUIT
CMOS INTEGRATED CIRCUIT AND METHOD FOR FORMING SOURCE/DRAIN AREAS PRIOR TO FORMING LIGHTLY DOPED DRAINS TO OPTIMIZE THE THERMAL DIFFUSIVITY THEREOF
CMOS INTEGRATED CIRCUIT AND METHOD FOR IMPLANTING NMOS TRANSISTOR AREAS PRIOR TO IMPLANTING PMOS TRANSISTOR AREAS TO OPTIMIZE THE THERMAL DIFFUSIVITY THEREOF
CMOS INTEGRATED CIRCUIT AND TIMING SIGNAL GENERATOR USING SAME
CMOS INTEGRATED CIRCUIT ARCHITECTURE INCORPORATING DEEP IMPLANTED EMITTER REGION TO FORM AUXILIARY BIPOLAR TRANSISTOR
CMOS INTEGRATED CIRCUIT DEVICE AND DATA PROCESSING SYSTEM USING THE SAME
CMOS INTEGRATED CIRCUIT DEVICE AND INSPECTION METHOD THEREOF
CMOS INTEGRATED CIRCUIT DEVICE AND ITS INSPECTING METHOD AND DEVICE
CMOS INTEGRATED CIRCUIT DEVICE WITH LDD N-CHANNEL TRANSISTOR AND NON-LDD P-CHANNEL TRANSISTOR
CMOS INTEGRATED CIRCUIT DEVICES AND SUBSTRATES HAVING UNSTRAINED SILICON ACTIVE LAYERS
CMOS INTEGRATED CIRCUIT FAILURE DIAGNOSIS APPARATUS AND DIAGNOSTIC METHOD
CMOS INTEGRATED CIRCUIT FOR LESSENING LATCH-UP SUSCEPTIBILITY
CMOS INTEGRATED CIRCUIT FORMED BY USING REMOVABLE SPACERS TO PRODUCE ASYMMETRICAL NMOS JUNCTIONS BEFORE ASYMMETRICAL PMOS JUNCTIONS FOR OPTIMIZING THERMAL DIFFUSIVITY OF DOPANTS IMPLANTED THEREIN
CMOS INTEGRATED CIRCUIT HAVING A SACRIFICIAL METAL SPACER FOR PRODUCING GRADED NMOS SOURCE/DRAIN JUNCTIONS DISSIMILAR FROM PMOS SOURCE/DRAIN JUNCTIONS
CMOS INTEGRATED CIRCUIT HAVING IMPROVED POWER-SUPPLY FILTERING
CMOS INTEGRATED CIRCUIT HAVING PMOS AND NMOS DEVICES WITH DIFFERENT GATE DIELECTRIC LAYERS
CMOS INTEGRATED CIRCUIT HAVING VERTICAL TRANSISTORS AND A PROCESS FOR FABRICATING SAME
CMOS INTEGRATED CIRCUIT INCLUDING FORMING DOPED WELLS, A LAYER OF INTRINSIC SILICON, A STRESSED SILICON GERMANIUM LAYER WHERE GERMANIUM IS BETWEEN 25 AND 50%, AND ANOTHER INTRINSIC SILICON LAYER
CMOS INTEGRATED CIRCUIT REGULATOR FOR REDUCING POWER SUPPLY NOISE
CMOS INTEGRATED CIRCUIT TESTING METHOD AND APPARATUS USING QUIESCENT POWER SUPPLY CURRENTS DATABASE
CMOS INTEGRATED CIRCUIT WITH REDUCED SUSCEPTIBILITY TO PMOS PUNCHTHROUGH
CMOS INTEGRATED CIRCUITRY WITH HALO AND LDD REGIONS
CMOS INTEGRATED CIRCUITS INCLUDING SOURCE/DRAIN PLUG
CMOS INTEGRATED CIRCUITS WITH REDUCED SUBSTRATE DEFECTS
CMOS INTEGRATED MICROSENSOR WITH A PRECISION MEASUREMENT CIRCUIT
CMOS INTEGRATED MID-SUPPLY VOLTAGE GENERATOR
CMOS INTEGRATED SEMICONDUCTOR CIRCUIT
CMOS INTEGRATED SIGNAL DETECTION CIRCUIT WITH HIGH EFFICIENCY AND PERFORMANCE
CMOS INTEGRATION PROCESS HAVING VERTICAL CHANNEL
CMOS INTERFACE CIRCUIT FORMED IN SILICON-ON-INSULATOR SUBSTRATE
CMOS INTERFACE FOR COUPLING A LOW VOLTAGE INTEGRATED CIRCUIT WITH DEVICES POWERED AT A HIGHER SUPPLY VOLTAGE
CMOS INVERTER
CMOS INVERTER AND STANDARD CELL USING THE SAME
CMOS INVERTER CONFIGURED FROM DOUBLE GATE MOSFET AND METHOD OF FABRICATING SAME
CMOS INVERTER USING GATE INDUCED DRAIN LEAKAGE CURRENT
CMOS ISOLATION UTILIZING ENHANCED OXIDATION OF RECESSED POROUS SILICON FORMED BY LIGHT ION IMPLANTATION
CMOS LATCH AND REGISTER CIRCUITRY USING QUANTUM MECHANICAL TUNNELING STRUCTURES
CMOS LATCH DESIGN WITH SOFT ERROR IMMUNITY
CMOS LATCH HAVING A SELECTABLE FEEDBACK PATH
CMOS LATCHING COMPARATOR
CMOS LATCHUP SUPPRESSION BY LOCALIZED MINORITY CARRIER LIFETIME REDUCTION
CMOS LEVEL CONVERSION CIRCUIT WITH INPUT PROTECTION
CMOS LEVEL DETECTION CIRCUIT WITH HYSTERESIS HAVING DISABLE/ENABLE FUNCTION AND METHOD
CMOS LEVEL SHIFT CIRCUIT FOR INTEGRATED CIRCUITS
CMOS LEVEL SHIFTER CIRCUIT
CMOS LEVEL SHIFTER WITH FEEDFORWARD CONTROL TO PREVENT LATCHING IN A WRONG LOGIC STATE
CMOS LEVEL SHIFTER WITH STEADY-STATE AND TRANSIENT DRIVERS
CMOS LEVEL SHIFTING CIRCUIT
CMOS LIMITED-VOLTAGE-SWING CLOCK DRIVER FOR REDUCED POWER DRIVING HIGH-FREQUENCY CLOCKS
CMOS LINEAR AMPLIFIER FORMED WITH NONLINEAR TRANSISTORS
CMOS LOCK DETECT WITH DOUBLE PROTECTION
CMOS LOCOS ISOLATION FOR SELF-ALIGNED NPN BJT IN A BICMOS PROCESS
CMOS LOGIC CELL FOR HIGH-SPEED, ZERO-POWER PROGRAMMABLE ARRAY LOGIC DEVICES
CMOS LOGIC CIRCUIT AND METHOD OF DRIVING THE SAME
CMOS LOGIC CIRCUIT WITH OUTPUT COUPLED TO MULTIPLE FEEDBACK PATHS AND ASSOCIATED METHOD
CMOS LOGIC CIRCUIT WITH PLURAL INPUTS
CMOS LOGIC CIRCUIT WITH REDUCED CIRCUIT AREA
CMOS LOGIC CIRCUITRY PROVIDING IMPROVED OPERATING SPEED
CMOS LOGIC CIRCUITS HAVING LOW AND HIGH-THRESHOLD VOLTAGE TRANSISTORS
CMOS LOGIC GATE CLAMPING CIRCUIT
CMOS LOGIC GATE HAVING BURIED CHANNEL NMOS TRANSISTOR FOR SEMICONDUCTOR DEVICES AND FABRICATION METHOD OF THE SAME
CMOS LOGIC LSI HAVING A LONG INTERNAL WIRING CONDUCTOR FOR SIGNAL TRANSMISSION
CMOS LOW BATTERY VOLTAGE DETECTOR
CMOS LOW NOISE AMPLIFIER
CMOS LOW OUTPUT VOLTAGE BUS DRIVER
CMOS LOW OUTPUT VOLTAGE BUS DRIVER WITH CONTROLLED CLAMPS
CMOS LOW POWER MIXED VOLTAGE BIDIRECTIONAL I/O BUFFER
CMOS LOW VOLTAGE CURRENT REFERENCE
CMOS LOW-POWER, WIDE-LINEAR-RANGE, WELL-INPUT DIFFERENTIAL AND TRANSCONDUCTANCE AMPLIFIERS
CMOS LOW-VOLTAGE COMPARATOR
CMOS LOW-VOLTAGE DYNAMIC BACK-GATE FORWARD BIAS PRESCALER
CMOS LOW-VOLTAGE FOUR-QUADRANT MULTIPLIER
CMOS LOW-VOLTAGE PECL DRIVER WITH INITIAL CURRENT BOOST
CMOS MAJORITY CIRCUIT
CMOS MANUFACTURING PROCESS WITH SELF-AMORPHIZED SOURCE/DRAIN JUNCTIONS AND EXTENSIONS
CMOS MASTER SLICE
CMOS MEMORY CELL
CMOS MEMORY CELL ARRAY
CMOS MEMORY CELL WITH GATE OXIDE OF BOTH NMOS AND PMOS TRANSISTORS AS TUNNELING WINDOW FOR PROGRAM AND ERASE
CMOS MEMORY CELL WITH IMPROVED READ PORT
CMOS MEMORY CELL WITH TUNNELING DURING PROGRAM AND ERASE THROUGH THE NMOS AND PMOS TRANSISTORS AND A PASS GATE SEPARATING THE NMOS AND PMOS TRANSISTORS
CMOS MEMORY DEVICE WITH IMPROVED SENSE AMPLIFIER BIASING
CMOS MICROWAVE MULTIPHASE VOLTAGE CONTROLLED OSCILLATOR
CMOS MULTIPLEXOR
CMOS OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
CMOS OFF CHIP DRIVER CIRCUIT
CMOS OFF CHIP DRIVER FOR FAULT TOLERANT COLD SPARING
CMOS OFF-CHIP DRIVER CIRCUIT
CMOS OFF-CHIP DRIVER CIRCUITS
CMOS OFF-CHIP DRIVER WITH REDUCED SIGNAL SWING AND REDUCED POWER SUPPLY DISTURBANCE
CMOS OFFSET TRIMMING CIRCUIT AND OFFSET GENERATION CIRCUIT
CMOS ON-CHIP ESD PROTECTION CIRCUIT AND SEMICONDUCTOR STRUCTURE
CMOS ON-CHIP FOUR-LVTSCR ESD PROTECTION SCHEME
CMOS ON-CHIP PRECISION VOLTAGE REFERENCE SCHEME
CMOS OP-AMP CIRCUIT USING BJT AS INPUT STAGE
CMOS OPAMP WITH LARGE SINKING AND SOURCING CURRENTS AND HIGH SLEW RATE
CMOS OPERATIONAL AMPLIFIER
CMOS OPERATIONAL AMPLIFIER CIRCUIT
CMOS OPERATIONAL AMPLIFIER WITH IMPROVED RAIL-TO-RAIL PERFORMANCE
CMOS OPERATIONAL AMPLIFIERS HAVING REDUCED POWER CONSUMPTION REQUIREMENTS AND IMPROVED PHASE MARGIN CHARACTERISTICS
CMOS OPTIMIZATION METHOD UTILIZING SACRIFICIAL SIDEWALL SPACER
CMOS OR TTL TO ECL LEVEL CONVERSION DEVICE
CMOS OUTPUT AMPLIFIER INDEPENDENT OF TEMPERATURE, SUPPLY VOLTAGE AND MANUFACTURING QUALITY OF TRANSISTORS
CMOS OUTPUT BUFFER CIRCUIT EXHIBITING REDUCED SWITCHING NOISE
CMOS OUTPUT BUFFER CIRCUIT WHICH CONVERTS CMOS LOGIC SIGNALS TO ECL LOGIC SIGNALS AND WHICH DISCHARGES PARASITIC LOAD CAPACITANCES
CMOS OUTPUT BUFFER CIRCUIT WITH IMPROVED GROUND BOUNCE
CMOS OUTPUT BUFFER CIRCUIT WITH LESS NOISE
CMOS OUTPUT BUFFER HAVING A HIGH CURRENT DRIVING CAPABILITY WITH LOW NOISE
CMOS OUTPUT BUFFER HAVING A SWITCHABLE BULK LINE
CMOS OUTPUT BUFFER HAVING LOAD INDEPENDENT SLEWING
CMOS OUTPUT BUFFER PROTECTION CIRCUIT
CMOS OUTPUT BUFFER WITH CMOS-CONTROLLED LATERAL SCR DEVICES
CMOS OUTPUT BUFFER WITH ENHANCED ESD RESISTANCE
CMOS OUTPUT BUFFER WITH ENHANCED HIGH ESD PROTECTION CAPABILITY
CMOS OUTPUT BUFFER WITH FEEDBACK CONTROL ON SOURCES OF PRE-DRIVER STAGE
CMOS OUTPUT BUFFER WITH NEGATIVE FEEDBACK DYNAMIC-DRIVE CONTROL AND DUAL P,N ACTIVE-TERMINATION TRANSMISSION GATES
CMOS OUTPUT BUFFER WITH PRE-DRIVE CIRCUITRY TO CONTROL SLEW RATE OF MAIN DRIVE TRANSISTORS
CMOS OUTPUT BUFFER WITH REDUCED L-DI/DT NOISE
CMOS OUTPUT BUFFER WITH SLEW RATE CONTROL
CMOS OUTPUT CIRCUIT COMPENSATING FOR BACK-GATE BIAS EFFECTS
CMOS OUTPUT CIRCUIT HAVING CONTROLLED SLOPE
CMOS OUTPUT CIRCUIT WITH ENHANCED ESD PROTECTION USING DRAIN SIDE IMPLANTATION
CMOS OUTPUT CIRCUIT WITH HIGH SPEED HIGH IMPEDANCE MODE
CMOS OUTPUT CIRCUIT WITH OPEN DRAIN TRANSISTOR
CMOS OUTPUT CIRCUIT WITH PRECHARGE CIRCUIT
CMOS OUTPUT DRIVER FOR SEMICONDUCTOR DEVICE AND RELATED METHOD FOR IMPROVING LATCH-UP IMMUNITY IN A CMOS OUTPUT DRIVER
CMOS OUTPUT DRIVER THAT CAN TOLERANT A HIGH INPUT VOLTAGE
CMOS OUTPUT DRIVER WHICH CAN TOLERATE AN OUTPUT VOLTAGE GREATER THAN THE SUPPLY VOLTAGE WITHOUT LATCHUP OR INCREASED LEAKAGE CURRENT
CMOS OUTPUT DRIVER WITH P-CHANNEL SUBSTRATE TRACKING FOR COLD SPARE CAPABILITY
CMOS OUTPUT DRIVER WITH SLEW RATE CONTROL
CMOS OUTPUT DRIVER WITH TRANSITION TIME CONTROL CIRCUIT
CMOS OUTPUT PAD DRIVER WITH VARIABLE DRIVE CURRENTS ESD PROTECTION AND IMPROVED LEAKAGE CURRENT BEHAVIOR
CMOS OUTPUT PULL-UP DRIVER
CMOS OUTPUT STAGE FOR PROVIDING STABLE QUIESCENT CURRENT
CMOS OVER VOLTAGE-TOLERANT OUTPUT BUFFER WITHOUT TRANSMISSION GATE
CMOS PASS TRANSISTOR LOGIC CIRCUITRY USING QUANTUM MECHANICAL TUNNELING STRUCTURES
CMOS PASSIVE INPUT CIRCUIT
CMOS PEAK AMPLITUDE DETECTOR
CMOS PECL DRIVER WITH PROGRAMMABLE CURRENT FOR VARYING VOLTAGE SWINGS AND TERMINATION TYPES
CMOS PHASE LOCKED LOOP WITH VOLTAGE CONTROLLED OSCILLATOR HAVING REALIGNMENT TO REFERENCE AND METHOD FOR THE SAME
CMOS PHOTODETECTORS WITH WIDE RANGE OPERATING REGION
CMOS PHOTODIODE HAVING REDUCED DARK CURRENT AND IMPROVED LIGHT SENSITIVITY AND RESPONSIVITY
CMOS PIXEL CELL FOR IMAGE DISPLAY SYSTEMS
CMOS POWER AMPLIFIER
CMOS POWER AMPLIFIER FOR DRIVING LOW IMPEDANCE LOADS
CMOS POWER AMPLIFIER WITH REDUCED HARMONICS AND IMPROVED EFFICIENCY
CMOS POWER DEVICE AND METHOD OF CONSTRUCTION AND LAYOUT
CMOS POWER FET DRIVER INCLUDING MULTIPLE POWER MOSFET TRANSISTORS CONNECTED IN PARALLEL, EACH CARRYING AN EQUIVALENT PORTION OF THE TOTAL DRIVER CURRENT
CMOS POWER SUPPLY VOLTAGE LIMITER
CMOS POWER-ON RESET CIRCUIT
CMOS POWER-ON RESET CIRCUIT USING HYSTERESIS
CMOS PREFERRED STATE POWER-UP LATCH
CMOS PROCESS
CMOS PROCESS AND CIRCUIT INCLUDING ZERO THRESHOLD TRANSISTORS
CMOS PROCESS COMPATIBLE SELF-ALIGNMENT LATERAL BIPOLAR JUNCTION TRANSISTOR
CMOS PROCESS COMPENSATION CIRCUIT
CMOS PROCESS FOR DOUBLE VERTICAL CHANNEL THIN FILM TRANSISTOR
CMOS PROCESS FOR FORMING PLANARIZED TWIN WELLS
CMOS PROCESS FORMING WELLS AFTER GATE FORMATION
CMOS PROCESS UTILIZING DISPOSABLE SILICON NITRIDE SPACERS FOR MAKING LIGHTLY DOPED DRAIN
CMOS PROCESS WITH AN INTEGRATED, HIGH PERFORMANCE, SILICIDE AGGLOMERATION FUSE
CMOS PROCESSING EMPLOYING REMOVABLE SIDEWALL SPACERS FOR INDEPENDENTLY OPTIMIZED N- AND P-CHANNEL TRANSISTOR PERFORMANCE
CMOS PROCESSING EMPLOYING SEPARATE SPACERS FOR INDEPENDENTLY OPTIMIZED TRANSISTOR PERFORMANCE
CMOS PROCESSING EMPLOYING ZERO DEGREE HALO IMPLANT FOR P-CHANNEL TRANSISTOR
CMOS PROCESSING WITH LOW AND HIGH-CURRENT FETS
CMOS PROCESSS WITH LOW THERMAL BUDGET
CMOS PROGRAMMABLE RESISTOR-BASED TRANSCONDUCTOR
CMOS PSEUDO-NMOS PROGRAMMABLE CAPACITANCE TIME VERNIER AND METHOD OF CALIBRATION
CMOS PULL-UP INPUT NETWORK
CMOS PULSE DELAY CIRCUIT
CMOS PULSE SHRINKING DELAY ELEMENT WITH DEEP SUBNANOSECOND RESOLUTION
CMOS RADIO FREQUENCY AMPLIFIER WITH INVERTER DRIVER
CMOS RAIL-TO-RAIL INPUT/OUTPUT AMPLIFIER
CMOS RC EQUIVALENT DELAY CIRCUIT
CMOS READ ONLY MEMORY WITH PROGRAMMING AT THE SECOND METAL LAYER ON A TWO-METAL PROCESS
CMOS RECEIVER CIRCUIT
CMOS REFERENCE CIRCUIT USING FIELD EFFECT TRANSISTORS IN LIEU OF RESISTORS AND DIODES
CMOS REFERENCE VOLTAGE GENERATOR
CMOS RELAXATION OSCILLATOR CIRCUIT WITH IMPROVED SPEED AND REDUCED PROCESS TEMPERATURE VARIATIONS
CMOS SELF-ADJUSTING BIAS GENERATOR FOR HIGH VOLTAGE DRIVERS
CMOS SELF-ALIGNED STRAPPED INTERCONNECTION
CMOS SEMICONDUCTOR CIRCUIT FOR GENERATING HIGH OUTPUT VOLTAGE
CMOS SEMICONDUCTOR CIRCUIT WITH REVERSE BIAS APPLIED FOR REDUCED POWER CONSUMPTION
CMOS SEMICONDUCTOR DEVICE
CMOS SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
CMOS SEMICONDUCTOR DEVICE COMPRISING GRADED JUNCTIONS WITH REDUCED JUNCTION CAPACITANCE
CMOS SEMICONDUCTOR DEVICE COMPRISING GRADED N-LDD JUNCTIONS WITH INCREASED HCI LIFETIME
CMOS SEMICONDUCTOR DEVICE CONTAINING N-CHANNEL TRANSISTOR HAVING SHALLOW LDD JUNCTIONS
CMOS SEMICONDUCTOR DEVICE HAVING BORON DOPED CHANNEL
CMOS SEMICONDUCTOR DEVICE HAVING DUAL-GATE ELECTRODE CONSTRUCTION AND METHOD OF PRODUCTION OF THE SAME
CMOS SEMICONDUCTOR DEVICE WITH (LDD) NMOS AND SINGLE DRAIN PMOS
CMOS SEMICONDUCTOR DEVICE WITH AN ELEMENT ISOLATING FIELD SHIELD
CMOS SEMICONDUCTOR DEVICE WITH IMPROVED LAYOUT OF TRANSISTORS NEAR LCD DRIVE TERMINALS
CMOS SEMICONDUCTOR DEVICES AND METHOD OF FORMATION
CMOS SEMICONDUCTOR INTEGRATED CIRCUIT
CMOS SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
CMOS SEMICONDUCTOR LOGIC CIRCUIT WITH MULTIPLE INPUT GATES
CMOS SEMICONDUCTOR STRUCTURE AND PROCESS FOR PRODUCING THE SAME
CMOS SENSE AMPLIFIER
CMOS SENSE AMPLIFIER WITH BIT LINE ISOLATION
CMOS SENSE STRUCTURE HAVING SILICON DIOXIDE OUTER RING AROUND SENSE REGION
CMOS SENSOR
CMOS SENSOR AND METHOD OF MANUFACTURE
CMOS SENSOR CAMERA WITH ON-CHIP IMAGE COMPRESSION
CMOS SENSOR HAVING A STRUCTURE TO REDUCE WHITE PIXELS
CMOS SENSOR HAVING ANALOG DELAY LINE FOR IMAGE PROCESSING
CMOS SENSOR STRUCTURE AND MANUFACTURING METHOD THEREOF
CMOS SENSOR WITH SHALLOW AND DEEP REGIONS
CMOS SEQUENTIAL LOGIC CONFIGURATION FOR AN EDGE TRIGGERED FLIP-FLOP
CMOS SHIFT REGISTER WITH COMPLEMENTARY REFRESH PASS GATES AND BUFFER
CMOS SIDEWALL OXIDE-LIGHTLY DOPED DRAIN PROCESS
CMOS SIMULTANEOUS TRANSMISSION BIDIRECTIONAL DRIVER/RECEIVER
CMOS SINGLE INPUT BUFFER FOR MULTIPLEXED INPUTS
CMOS SINGLE PHASE REGISTERS
CMOS SKEWED STATIC LOGIC AND METHOD OF SYNTHESIS
CMOS SMALL SIGNAL SWITCHABLE ADJUSTABLE IMPEDENCE TERMINATOR NETWORK
CMOS SMALL SIGNAL SWITCHABLE IMPEDENCE AND VOLTAGE ADJUSTABLE TERMINATOR WITH HYSTERESIS RECEIVER NETWORK
CMOS SMALL SIGNAL SWITCHABLE TERMINATOR NETWORK
CMOS SMALL SIGNAL SWITCHABLE, IMPEDENCE AND VOLTAGE ADJUSTABLE TERMINATOR NETWORK
CMOS SMALL SIGNAL SWITCHABLE, IMPEDENCE AND VOLTAGE ADJUSTABLE TERMINATOR NETWORK AND RECEIVER INTEGRATION
CMOS SMALL SIGNAL TERMINATED HYSTERESIS RECEIVER
CMOS SMALL SIGNAL TERMINATED RECEIVER
CMOS SMALL SIGNAL TERMINATOR AND NETWORK
CMOS SOFT CLIPPER
CMOS SOI CONTACT INTEGRITY TEST METHOD
CMOS SONET/ATM RECEIVER SUITABLE FOR USE WITH PSEUDO ECL AND TTL SIGNALING ENVIRONMENTS
CMOS SRAM CELL
CMOS SRAM CELL WITH PFET PASSGATE DEVICES
CMOS SRAM CELL WITH PRESCRIBED POWER-ON DATA STATE
CMOS STATE SAVING LATCH
CMOS STATIC LOGIC CIRCUIT
CMOS STATIC MEMORY
CMOS STATIC RAM TESTABILITY
CMOS STATIC RANDOM ACCESS MEMORY DEVICES
CMOS STROBED COMPARATOR
CMOS STROBED COMPARATOR WITH PROGRAMMABLE HYSTERESIS
CMOS STRUCTURE FABRICATION
CMOS STRUCTURE FOR ELIMINATING LATCH-UP OF PARASITIC THYRISTOR
CMOS STRUCTURE HAVING A GATE WITHOUT SPACERS
CMOS STRUCTURE HAVING DYNAMIC THRESHOLD VOLTAGE
CMOS STRUCTURE WITH FETS HAVING ISOLATED WELLS WITH MERGED DEPLETIONS AND METHODS OF MAKING SAME
CMOS STRUCTURE WITH NON-EPITAXIAL RAISED SOURCE/DRAIN AND SELF-ALIGNED GATE AND METHOD OF MANUFACTURE | CMOS STRUCTURE WITH PARASITIC CHANNEL PREVENTION
CMOS STRUCTURE WITH VARYING GATE OXIDE THICKNESS AND WITH BOTH DIFFERENT AND LIKE CONDUCTIVITY-TYPE GATE ELECTRODES
CMOS SUB-BANDGAP REFERENCE WITH AN OPERATING SUPPLY VOLTAGE LESS THAN THE BANDGAP
CMOS SUBSTRATE BIASING FOR THRESHOLD VOLTAGE CONTROL
CMOS SUM SELECT INCREMENTOR
CMOS SWITCH CIRCUIT FOR TRANSFERRING HIGH VOLTAGES, IN PARTICULAR FOR LINE DECODING IN NONVOLATILE MEMORIES, WITH REDUCED CONSUMPTION DURING SWITCHING
CMOS SWITCH CIRCUIT HAVING CONCURRENTLY SWITCHING COMPLEMENTARY OUTPUTS INDEPENDENT FROM PROCESS VARIATION
CMOS SWITCH WITH LINEARIZED GATE CAPACITANCE
CMOS SWITCHING CIRCUITRY
CMOS TECHNOLOGY HIGH SPEED DIGITAL SIGNAL TRANSCEIVER
CMOS TECHNOLOGY VOLTAGE BOOSTER
CMOS TEMPERATURE SENSOR
CMOS TERMINATING RESISTOR CIRCUIT
CMOS THIN-FILM TRANSISTOR HAVING SPLIT GATE STRUCTURE
CMOS TO ECL LEVEL TRANSLATOR
CMOS TO ECL TRANSLATOR CIRCUIT AND METHODOLOGY
CMOS TO ECL TRANSLATOR WITH INCORPORATED LATCH
CMOS TO ECL/CML LEVEL CONVERTER
CMOS TOGGLE FLIP-FLOP USING ADIABATIC SWITCHING
CMOS TRACK AND HOLD AMPLIFIER
CMOS TRANSCEIVER HAVING AN INTEGRATED POWER AMPLIFIER
CMOS TRANSCONDUCTANCE AMPLIFIER WITH FLOATING OPERATING POINT
CMOS TRANSCONDUCTOR CIRCUIT WITH HIGH LINEARITY
CMOS TRANSCONDUCTOR WITH INCREASED DYNAMIC RANGE
CMOS TRANSISTOR AND ISOLATED BACK GATE ELECTRODES ON AN SOI SUBSTRATE
CMOS TRANSISTOR AND METHOD OF FABRICATING THE SAME
CMOS TRANSISTOR DESIGN FOR SHARED N+/P+ ELECTRODE WITH ENHANCED DEVICE PERFORMANCE
CMOS TRANSISTOR NETWORK TO GATE LEVEL MODEL EXTRACTOR FOR SIMULATION, VERIFICATION AND TEST GENERATION
CMOS TRANSISTOR WITH AMORPHOUS SILICON ELEVATED SOURCE-DRAIN STRUCTURE AND METHOD OF FABRICATION
CMOS TRANSISTOR WITH TWO CHANNEL REGIONS AND COMMON GATE
CMOS TRANSISTOR WITH TWO-LAYER INVERSE-T TUNGSTEN GATE
CMOS TRANSISTORS FABRICATED IN OPTIMIZED RTA SCHEME
CMOS TRANSISTORS WITH SELF-ALIGNED PLANARIZATION TWIN-WELL BY USING FEWER MASK COUNTS
CMOS TRANSMISSION GATE WITH HIGH IMPEDANCE AT POWER OFF
CMOS TRI-MODE INPUT BUFFER
CMOS TRI-STATE BUFFER CIRCUIT AND OPERATION METHOD THEREOF
CMOS TRI-STATE CONTROL CIRCUIT FOR A BIDIRECTIONAL I/O WITH SLEW RATE CONTROL
CMOS TRIGGERED NMOS ESD PROTECTION CIRCUIT
CMOS TRISTATE OUTPUT BUFFER WITH HAVING OVERVOLTAGE PROTECTION AND INCREASED STABILITY AGAINST BUS VOLTAGE VARIATIONS
CMOS TRISTATEABLE BUFFER
CMOS TWIN-TUB NEGATIVE VOLTAGE SWITCHING ARCHITECTURE
CMOS TYPE INPUT BUFFER CIRCUIT FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE WITH THE SAME
CMOS TYPE SOLID IMAGING DEVICE
CMOS VARIABLE GAIN AMPLIFIER AND CONTROL METHOD THEREFOR
CMOS VERTICAL REPLACEMENT GATE (VRG) TRANSISTORS
CMOS VOLTAGE CLAMP
CMOS VOLTAGE COMPARATOR CAPABLE OF OPERATING WITH SMALL INPUT VOLTAGE DIFFERENCE
CMOS VOLTAGE CONTROLLED OSCILLATOR
CMOS VOLTAGE CONTROLLED PHASE SHIFT OSCILLATOR
CMOS VOLTAGE CONTROLLED RING OSCILLATOR
CMOS VOLTAGE DIVIDER
CMOS VOLTAGE LEVEL TRANSLATOR CIRCUIT
CMOS VOLTAGE REFERENCE
CMOS VOLTAGE REFERENCE CIRCUIT
CMOS VOLTAGE REFERENCE WITH A NULLING AMPLIFIER
CMOS VOLTAGE REFERENCE WITH POST-ASSEMBLY CURVATURE TRIM
CMOS VOLTAGE REFERENCE WITH STACKED BASE-TO-EMITTER VOLTAGES
CMOS VOLTAGE REGULATOR
CMOS VOLTAGE REGULATOR WITH DIODE-CONNECTED TRANSISTOR DIVIDER CIRCUIT
CMOS VOLTAGE SHIFTER
CMOS WAVESHAPING BUFFER
CMOS WELL SWITCHING CIRCUIT
CMOS WHOLE CHIP LOW CAPACITANCE ESD PROTECTION CIRCUIT
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