PIPELINE BURST CACHE

Domain	Definition
Computing	Pipeline Burst Cache (PB Cache) A synchronous cache built from pipelined SRAM. A cache in which reading or writing a new location takes multiple cycles but subsequent locations can be accessed in a single cycle. On Pentium systems in 1996, pipeline burst caches are frequently used as secondary caches. The first 8 bytes of data are transferred in 3 CPU cycles, and the next 3 8-byte pieces of data are transferred in one cycle each. (1996-10-13). Source: The Free On-line Dictionary of Computing.
Source: compiled by the editor from various references; see credits.

Anagrams: PIPELINE BURST CACHE

Scrabble® Enable2K-Verified Anagrams
	Words within the letters "a-b-c-c-e-e-e-h-i-i-l-n-p-p-r-s-t-u"
	-5 letters: apprehensible, precipitances, unrespectable.
Source: compiled by the editor from various references; see credits. SCRABBLE® is a registered trademark. All intellectual property rights in and to the game are owned in the U.S.A and Canada by Hasbro Inc., and throughout the rest of the world by J.W. Spear & Sons Limited of Maidenhead, Berkshire, England, a subsidiary of Mattel Inc. Mattel and Spear are not affiliated with Hasbro.

Alternative Orthography: PIPELINE BURST CACHE

Hexadecimal (or equivalents, 770AD-1900s) (references)

Leonardo da Vinci (1452-1519; backwards) (references)

Binary Code (1918-1938, probably earlier) (references)

HTML Code (1990) (references)

ISO 10646 (1991-1993) (references)

Encryption (beginner's substitution cypher): (references)

Specialty Definition: PIPELINE BURST CACHE